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m68k.c: Include <stdlib.h> for atoi. 

* config/m68k/m68k.c: Include <stdlib.h> for atoi.  Include
	"recog.h" for offsettable_memref_p.
	(legitimize_pic_address): Remove unused variable `offset'.
	(notice_update_cc): Change return type to void.  Add default label
	to switch.
	(standard_68881_constant_p): Remove unused variable mode.
	(print_operand): Define local variable i only if SUPPORT_SUN_FPA.
	(const_int_cost): Explicitly declare as returning int.
	(output_dbcc_and_branch): Change return type to void.
	* config/m68k/linux.h, config/m68k/m68k.md, config/m68k/m68k.c,
	config/m68k/m68k.h: Replace gen_rtx (XXX, ...) with gen_rtx_XXX
	(...).  Use GEN_INT instead of gen_rtx_CONST_INT.

From-SVN: r18617
This commit is contained in:
Andreas Schwab 1998-03-16 02:16:43 +00:00 committed by Andreas Schwab
parent 60ba47b43c
commit 1d8eaa6b15
5 changed files with 195 additions and 192 deletions
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16
gcc/ChangeLog
View File

@ -1,3 +1,19 @@
Mon Mar 16 11:14:20 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
* config/m68k/m68k.c: Include <stdlib.h> for atoi. Include
"recog.h" for offsettable_memref_p.
(legitimize_pic_address): Remove unused variable `offset'.
(notice_update_cc): Change return type to void. Add default label
to switch.
(standard_68881_constant_p): Remove unused variable mode.
(print_operand): Define local variable i only if SUPPORT_SUN_FPA.
(const_int_cost): Explicitly declare as returning int.
(output_dbcc_and_branch): Change return type to void.
* config/m68k/linux.h, config/m68k/m68k.md, config/m68k/m68k.c,
config/m68k/m68k.h: Replace gen_rtx (XXX, ...) with gen_rtx_XXX
(...). Use GEN_INT instead of gen_rtx_CONST_INT.
Sun Mar 15 22:30:44 PST 1998 Jeff Law (law@cygnus.com)
* version.c: Bump for snapshot.

12
gcc/config/m68k/linux.h
View File

@ -270,10 +270,10 @@ Boston, MA 02111-1307, USA. */
#undef FUNCTION_VALUE
#define FUNCTION_VALUE(VALTYPE, FUNC) \
(TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_68881 \
? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
? gen_rtx_REG (TYPE_MODE (VALTYPE), 16) \
: (POINTER_TYPE_P (VALTYPE) \
? gen_rtx (REG, TYPE_MODE (VALTYPE), 8) \
: gen_rtx (REG, TYPE_MODE (VALTYPE), 0)))
? gen_rtx_REG (TYPE_MODE (VALTYPE), 8) \
: gen_rtx_REG (TYPE_MODE (VALTYPE), 0)))
/* For compatibility with the large body of existing code which does
not always properly declare external functions returning pointer
@ -299,8 +299,8 @@ do { \
#define LIBCALL_VALUE(MODE) \
((((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode) \
&& TARGET_68881) \
? gen_rtx (REG, (MODE), 16) \
: gen_rtx (REG, (MODE), 0))
? gen_rtx_REG (MODE, 16) \
: gen_rtx_REG (MODE, 0))
/* In m68k svr4, a symbol_ref rtx can be a valid PIC operand if it is
an operand of a function call. */
@ -330,7 +330,7 @@ do { \
#undef FINALIZE_TRAMPOLINE
#define FINALIZE_TRAMPOLINE(TRAMP) \
emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__clear_cache"), \
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
0, VOIDmode, 2, TRAMP, Pmode, \
plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode);

94
gcc/config/m68k/m68k.c
View File

@ -32,10 +32,15 @@ Boston, MA 02111-1307, USA. */
#include "insn-flags.h"
#include "output.h"
#include "insn-attr.h"
#include "recog.h"
/* Needed for use_return_insn. */
#include "flags.h"
#if HAVE_STDLIB_H
#include <stdlib.h>
#endif
#ifdef SUPPORT_SUN_FPA
/* Index into this array by (register number >> 3) to find the
@ -135,7 +140,7 @@ finalize_pic ()
{
if (flag_pic && current_function_uses_pic_offset_table)
{
rtx insn = gen_rtx (USE, VOIDmode, pic_offset_table_rtx);
rtx insn = gen_rtx_USE (VOIDmode, pic_offset_table_rtx);
emit_insn_after (insn, get_insns ());
emit_insn (insn);
}
@ -892,6 +897,7 @@ flags_in_68881 ()
set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
kick those out before we get here. */
void
output_dbcc_and_branch (operands)
rtx *operands;
{
@ -1027,14 +1033,14 @@ output_scc_di(op, operand1, operand2, dest)
}
loperands[0] = operand1;
if (GET_CODE (operand1) == REG)
loperands[1] = gen_rtx (REG, SImode, REGNO (operand1) + 1);
loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
else
loperands[1] = adj_offsettable_operand (operand1, 4);
if (operand2 != const0_rtx)
{
loperands[2] = operand2;
if (GET_CODE (operand2) == REG)
loperands[3] = gen_rtx (REG, SImode, REGNO (operand2) + 1);
loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
else
loperands[3] = adj_offsettable_operand (operand2, 4);
}
@ -1308,9 +1314,9 @@ legitimize_pic_address (orig, mode, reg)
if (reg == 0)
abort ();
pic_ref = gen_rtx (MEM, Pmode,
gen_rtx (PLUS, Pmode,
pic_offset_table_rtx, orig));
pic_ref = gen_rtx_MEM (Pmode,
gen_rtx_PLUS (Pmode,
pic_offset_table_rtx, orig));
current_function_uses_pic_offset_table = 1;
if (reload_in_progress)
regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
@ -1320,7 +1326,7 @@ legitimize_pic_address (orig, mode, reg)
}
else if (GET_CODE (orig) == CONST)
{
rtx base, offset;
rtx base;
/* Make sure this is CONST has not already been legitimized */
if (GET_CODE (XEXP (orig, 0)) == PLUS
@ -1341,7 +1347,7 @@ legitimize_pic_address (orig, mode, reg)
if (GET_CODE (orig) == CONST_INT)
return plus_constant_for_output (base, INTVAL (orig));
pic_ref = gen_rtx (PLUS, Pmode, base, orig);
pic_ref = gen_rtx_PLUS (Pmode, base, orig);
/* Likewise, should we set special REG_NOTEs here? */
}
return pic_ref;
@ -1386,6 +1392,7 @@ const_method (constant)
return MOVL;
}
int
const_int_cost (constant)
rtx constant;
{
@ -1423,14 +1430,14 @@ output_move_const_into_data_reg (operands)
return "moveq %1,%0";
#endif
case NOTB :
operands[1] = gen_rtx (CONST_INT, VOIDmode, i ^ 0xff);
operands[1] = GEN_INT (i ^ 0xff);
#if defined (MOTOROLA) && !defined (CRDS)
return "moveq%.l %1,%0\n\tnot%.b %0";
#else
return "moveq %1,%0\n\tnot%.b %0";
#endif
case NOTW :
operands[1] = gen_rtx (CONST_INT, VOIDmode, i ^ 0xffff);
operands[1] = GEN_INT (i ^ 0xffff);
#if defined (MOTOROLA) && !defined (CRDS)
return "moveq%.l %1,%0\n\tnot%.w %0";
#else
@ -1446,7 +1453,7 @@ output_move_const_into_data_reg (operands)
{
unsigned u = i;
operands[1] = gen_rtx (CONST_INT, VOIDmode, (u << 16) | (u >> 16));
operands[1] = GEN_INT ((u << 16) | (u >> 16));
#if defined (MOTOROLA) && !defined (CRDS)
return "moveq%.l %1,%0\n\tswap %0";
#else
@ -1589,8 +1596,8 @@ output_move_qimode (operands)
{
xoperands[1] = operands[1];
xoperands[2]
= gen_rtx (MEM, QImode,
gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx));
= gen_rtx_MEM (QImode,
gen_rtx_PLUS (VOIDmode, stack_pointer_rtx, const1_rtx));
/* Just pushing a byte puts it in the high byte of the halfword. */
/* We must put it in the low-order, high-numbered byte. */
if (!reg_mentioned_p (stack_pointer_rtx, operands[1]))
@ -1757,11 +1764,11 @@ output_move_double (operands)
else
output_asm_insn ("subq%.l %#8,%0", operands);
if (GET_MODE (operands[1]) == XFmode)
operands[0] = gen_rtx (MEM, XFmode, operands[0]);
operands[0] = gen_rtx_MEM (XFmode, operands[0]);
else if (GET_MODE (operands[0]) == DFmode)
operands[0] = gen_rtx (MEM, DFmode, operands[0]);
operands[0] = gen_rtx_MEM (DFmode, operands[0]);
else
operands[0] = gen_rtx (MEM, DImode, operands[0]);
operands[0] = gen_rtx_MEM (DImode, operands[0]);
optype0 = OFFSOP;
}
if (optype0 == POPOP && optype1 == PUSHOP)
@ -1772,11 +1779,11 @@ output_move_double (operands)
else
output_asm_insn ("subq%.l %#8,%1", operands);
if (GET_MODE (operands[1]) == XFmode)
operands[1] = gen_rtx (MEM, XFmode, operands[1]);
operands[1] = gen_rtx_MEM (XFmode, operands[1]);
else if (GET_MODE (operands[1]) == DFmode)
operands[1] = gen_rtx (MEM, DFmode, operands[1]);
operands[1] = gen_rtx_MEM (DFmode, operands[1]);
else
operands[1] = gen_rtx (MEM, DImode, operands[1]);
operands[1] = gen_rtx_MEM (DImode, operands[1]);
optype1 = OFFSOP;
}
@ -1802,8 +1809,8 @@ output_move_double (operands)
{
if (optype0 == REGOP)
{
latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2);
middlehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
}
else if (optype0 == OFFSOP)
{
@ -1818,8 +1825,8 @@ output_move_double (operands)
if (optype1 == REGOP)
{
latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
middlehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
}
else if (optype1 == OFFSOP)
{
@ -1860,14 +1867,14 @@ output_move_double (operands)
/* size is not 12: */
{
if (optype0 == REGOP)
latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else if (optype0 == OFFSOP)
latehalf[0] = adj_offsettable_operand (operands[0], size - 4);
else
latehalf[0] = operands[0];
if (optype1 == REGOP)
latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else if (optype1 == OFFSOP)
latehalf[1] = adj_offsettable_operand (operands[1], size - 4);
else if (optype1 == CNSTOP)
@ -1892,7 +1899,7 @@ output_move_double (operands)
if (optype0 == REGOP
&& (optype1 == OFFSOP || optype1 == MEMOP))
{
rtx testlow = gen_rtx (REG, SImode, REGNO (operands[0]));
rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0]));
if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
&& reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
@ -1906,13 +1913,13 @@ compadr:
output_asm_insn ("lea %a1,%0", xops);
if( GET_MODE (operands[1]) == XFmode )
{
operands[1] = gen_rtx (MEM, XFmode, latehalf[0]);
operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
latehalf[1] = adj_offsettable_operand (operands[1], size-4);
}
else
{
operands[1] = gen_rtx (MEM, DImode, latehalf[0]);
operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
latehalf[1] = adj_offsettable_operand (operands[1], size-4);
}
}
@ -2115,8 +2122,7 @@ output_addsi3 (operands)
if (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) >= -8)
{
operands[2] = gen_rtx (CONST_INT, VOIDmode,
- INTVAL (operands[2]));
operands[2] = GEN_INT (-INTVAL (operands[2]));
return "subq%.l %2,%0";
}
/* On the CPU32 it is faster to use two addql instructions to
@ -2127,15 +2133,13 @@ output_addsi3 (operands)
if (INTVAL (operands[2]) > 8
&& INTVAL (operands[2]) <= 16)
{
operands[2] = gen_rtx (CONST_INT, VOIDmode,
INTVAL (operands[2]) - 8);
operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
return "addq%.l %#8,%0\n\taddq%.l %2,%0";
}
if (INTVAL (operands[2]) < -8
&& INTVAL (operands[2]) >= -16)
{
operands[2] = gen_rtx (CONST_INT, VOIDmode,
- INTVAL (operands[2]) - 8);
operands[2] = GEN_INT (-INTVAL (operands[2]) - 8);
return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
}
}
@ -2166,6 +2170,7 @@ output_addsi3 (operands)
possibly invalid to use the saved cc's. In those cases we clear out
some or all of the saved cc's so they won't be used. */
void
notice_update_cc (exp, insn)
rtx exp;
rtx insn;
@ -2263,6 +2268,9 @@ notice_update_cc (exp, insn)
Thus, the cc's are set for r2.
This can set N bit spuriously. */
cc_status.flags |= CC_NOT_NEGATIVE;
default:
break;
}
if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
&& cc_status.value2
@ -2401,7 +2409,6 @@ standard_68881_constant_p (x)
{
REAL_VALUE_TYPE r;
int i;
enum machine_mode mode;
#ifdef NO_ASM_FMOVECR
return 0;
@ -2694,7 +2701,9 @@ print_operand (file, op, letter)
rtx op; /* operand to print */
int letter; /* %<letter> or 0 */
{
#ifdef SUPPORT_SUN_FPA
int i;
#endif
if (letter == '.')
{
@ -3248,8 +3257,7 @@ output_andsi3 (operands)
{
if (GET_CODE (operands[0]) != REG)
operands[0] = adj_offsettable_operand (operands[0], 2);
operands[2] = gen_rtx (CONST_INT, VOIDmode,
INTVAL (operands[2]) & 0xffff);
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
/* Do not delete a following tstl %0 insn; that would be incorrect. */
CC_STATUS_INIT;
if (operands[2] == const0_rtx)
@ -3263,12 +3271,12 @@ output_andsi3 (operands)
{
if (DATA_REG_P (operands[0]))
{
operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
operands[1] = GEN_INT (logval);
}
else
{
operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
operands[1] = GEN_INT (logval % 8);
}
/* This does not set condition codes in a standard way. */
CC_STATUS_INIT;
@ -3303,12 +3311,12 @@ output_iorsi3 (operands)
{
if (DATA_REG_P (operands[0]))
{
operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
operands[1] = GEN_INT (logval);
}
else
{
operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
operands[1] = GEN_INT (logval % 8);
}
CC_STATUS_INIT;
return "bset %1,%0";
@ -3341,12 +3349,12 @@ output_xorsi3 (operands)
{
if (DATA_REG_P (operands[0]))
{
operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
operands[1] = GEN_INT (logval);
}
else
{
operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
operands[1] = GEN_INT (logval % 8);
}
CC_STATUS_INIT;
return "bchg %1,%0";

16
gcc/config/m68k/m68k.h
View File

@ -888,14 +888,14 @@ extern enum reg_class regno_reg_class[];
/* On the 68000 the return value is in D0 regardless. */
#define FUNCTION_VALUE(VALTYPE, FUNC) \
gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
/* Define how to find the value returned by a library function
assuming the value has mode MODE. */
/* On the 68000 the return value is in D0 regardless. */
#define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0)
#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
/* 1 if N is a possible register number for a function value.
On the 68000, d0 is the only register thus used. */
@ -965,7 +965,7 @@ extern enum reg_class regno_reg_class[];
It exists only to test register calling conventions. */
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0)
((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0)
/* For an arg passed partly in registers and partly in memory,
this is the number of registers used.
@ -1235,11 +1235,11 @@ while(0)
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
{ \
emit_move_insn (gen_rtx (MEM, HImode, TRAMP), GEN_INT(0x207C)); \
emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 2)), CXT); \
emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 6)), \
emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
GEN_INT(0x4EF9)); \
emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), FNADDR); \
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
FINALIZE_TRAMPOLINE(TRAMP); \
}
@ -1800,7 +1800,7 @@ __transfer_from_trampoline () \
/* Before the prologue, RA is at 0(%sp). */
#define INCOMING_RETURN_ADDR_RTX \
gen_rtx (MEM, VOIDmode, gen_rtx (REG, VOIDmode, STACK_POINTER_REGNUM))
gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
/* We must not use the DBX register numbers for the DWARF 2 CFA column
numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.

249
gcc/config/m68k/m68k.md
View File

@ -813,7 +813,7 @@
"(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
"*
{
operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
operands[1] = GEN_INT (7 - INTVAL (operands[1]));
return output_btst (operands, operands[1], operands[0], insn, 7);
}")
@ -828,12 +828,10 @@
{
operands[0] = adj_offsettable_operand (operands[0],
INTVAL (operands[1]) / 8);
operands[1] = gen_rtx (CONST_INT, VOIDmode,
7 - INTVAL (operands[1]) % 8);
operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
return output_btst (operands, operands[1], operands[0], insn, 7);
}
operands[1] = gen_rtx (CONST_INT, VOIDmode,
31 - INTVAL (operands[1]));
operands[1] = GEN_INT (31 - INTVAL (operands[1]));
return output_btst (operands, operands[1], operands[0], insn, 31);
}")
@ -851,12 +849,10 @@
{
operands[0] = adj_offsettable_operand (operands[0],
INTVAL (operands[1]) / 8);
operands[1] = gen_rtx (CONST_INT, VOIDmode,
7 - INTVAL (operands[1]) % 8);
operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
return output_btst (operands, operands[1], operands[0], insn, 7);
}
operands[1] = gen_rtx (CONST_INT, VOIDmode,
31 - INTVAL (operands[1]));
operands[1] = GEN_INT (31 - INTVAL (operands[1]));
return output_btst (operands, operands[1], operands[0], insn, 31);
}")
@ -1182,7 +1178,7 @@
if (REG_P (operands[1]))
{
rtx xoperands[2];
xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
output_asm_insn (\"move%.l %1,%-\", xoperands);
output_asm_insn (\"move%.l %1,%-\", operands);
return \"f%&move%.d %+,%0\";
@ -1196,7 +1192,7 @@
if (REG_P (operands[0]))
{
output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
return \"move%.l %+,%0\";
}
else
@ -1240,9 +1236,9 @@
if (REG_P (operands[1]))
{
rtx xoperands[2];
xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
output_asm_insn (\"move%.l %1,%-\", xoperands);
xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
output_asm_insn (\"move%.l %1,%-\", xoperands);
output_asm_insn (\"move%.l %1,%-\", operands);
return \"fmove%.x %+,%0\";
@ -1254,9 +1250,9 @@
if (REG_P (operands[0]))
{
output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
output_asm_insn (\"move%.l %+,%0\", operands);
operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
return \"move%.l %+,%0\";
}
return \"fmove%.x %f1,%0\";
@ -1276,9 +1272,9 @@
if (REG_P (operands[1]))
{
rtx xoperands[2];
xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
output_asm_insn (\"move%.l %1,%-\", xoperands);
xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
output_asm_insn (\"move%.l %1,%-\", xoperands);
output_asm_insn (\"move%.l %1,%-\", operands);
return \"fmove%.x %+,%0\";
@ -1292,9 +1288,9 @@
if (REG_P (operands[0]))
{
output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
output_asm_insn (\"move%.l %+,%0\", operands);
operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
return \"move%.l %+,%0\";
}
else
@ -1340,7 +1336,7 @@
if (REG_P (operands[1]))
{
rtx xoperands[2];
xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
output_asm_insn (\"move%.l %1,%-\", xoperands);
output_asm_insn (\"move%.l %1,%-\", operands);
return \"fmove%.d %+,%0\";
@ -1354,7 +1350,7 @@
if (REG_P (operands[0]))
{
output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
return \"move%.l %+,%0\";
}
else
@ -1458,7 +1454,7 @@
{
CC_STATUS_INIT;
if (GET_CODE (operands[0]) == REG)
operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
return \"move%.l %1,%0\;clr%.l %0\";
else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
@ -1481,10 +1477,10 @@
{
operands[1] = make_safe_from (operands[1], operands[0]);
if (GET_CODE (operands[0]) == SUBREG)
operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]),
SUBREG_WORD (operands[0]));
operands[2] = gen_rtx_SUBREG (HImode, SUBREG_REG (operands[0]),
SUBREG_WORD (operands[0]));
else
operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0);
operands[2] = gen_rtx_SUBREG (HImode, operands[0], 0);
}")
(define_expand "zero_extendqihi2"
@ -1497,10 +1493,10 @@
{
operands[1] = make_safe_from (operands[1], operands[0]);
if (GET_CODE (operands[0]) == SUBREG)
operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
SUBREG_WORD (operands[0]));
operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
SUBREG_WORD (operands[0]));
else
operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
}")
(define_expand "zero_extendqisi2"
@ -1513,10 +1509,10 @@
{
operands[1] = make_safe_from (operands[1], operands[0]);
if (GET_CODE (operands[0]) == SUBREG)
operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
SUBREG_WORD (operands[0]));
operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
SUBREG_WORD (operands[0]));
else
operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
}")
;; Patterns to recognize zero-extend insns produced by the combiner.
@ -1575,8 +1571,8 @@
== STACK_POINTER_REGNUM)
{
output_asm_insn (\"clr%.w %-\", operands);
operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
plus_constant (stack_pointer_rtx, 1));
operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
plus_constant (stack_pointer_rtx, 1));
return \"move%.b %1,%0\";
}
else
@ -1654,7 +1650,7 @@
"*
{
CC_STATUS_INIT;
operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
if (TARGET_68020 || TARGET_5200)
return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
else
@ -1669,7 +1665,7 @@
"*
{
CC_STATUS_INIT;
operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
if (TARGET_68020 || TARGET_5200)
return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
else
@ -1684,7 +1680,7 @@
"*
{
CC_STATUS_INIT;
operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
if (TARGET_68020 || TARGET_5200)
return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
else
@ -1703,7 +1699,7 @@
"*
{
CC_STATUS_INIT;
operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
if (GET_CODE (operands[1]) == CONST_INT
&& (unsigned) INTVAL (operands[1]) > 8)
{
@ -1787,7 +1783,7 @@
if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
{
output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
return \"move%.l %+,%0\";
}
return \"fmove%.d %f1,%0\";
@ -2028,12 +2024,12 @@
""
"*
{
operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
return
\"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
if (GET_CODE (operands[1]) == REG)
operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
|| GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
operands[4] = operands[1];
@ -2085,7 +2081,7 @@
{
CC_STATUS_INIT;
if (GET_CODE (operands[0]) == REG)
operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[2] = adj_offsettable_operand (operands[0], 4);
return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
@ -2104,7 +2100,7 @@
{
CC_STATUS_INIT;
if (GET_CODE (operands[1]) == REG)
operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else
operands[1] = adj_offsettable_operand (operands[1], 4);
return \"add%.l %1,%0\";
@ -2130,7 +2126,7 @@
else
{
if (GET_CODE (operands[2]) == REG)
operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
operands[1] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
else if (GET_CODE (operands[2]) == CONST_DOUBLE)
{
operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
@ -2155,9 +2151,10 @@
CC_STATUS_INIT;
if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
{
operands[1] = gen_rtx (MEM, SImode,
gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
gen_rtx (CONST_INT, VOIDmode, -8)));
operands[1]
= gen_rtx_MEM (SImode,
gen_rtx_PLUS (VOIDmode, XEXP(operands[0], 0),
GEN_INT (-8)));
return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
}
else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
@ -2186,9 +2183,9 @@
if (GET_CODE (operands[0]) == MEM)
{
if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
operands[0] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
operands[2] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
}
output_asm_insn (\"move%.l %1,%0\", operands);
#ifdef MOTOROLA
@ -2255,8 +2252,7 @@
which could confuse us. */
if (INTVAL (operands[2]) >= 32768)
operands[2] = gen_rtx (CONST_INT, VOIDmode,
INTVAL (operands[2]) - 65536);
operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
if (INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) <= 8)
@ -2264,8 +2260,7 @@
if (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) >= -8)
{
operands[2] = gen_rtx (CONST_INT, VOIDmode,
- INTVAL (operands[2]));
operands[2] = GEN_INT (-INTVAL (operands[2]));
return \"subq%.w %2,%0\";
}
/* On the CPU32 it is faster to use two addqw instructions to
@ -2276,15 +2271,13 @@
if (INTVAL (operands[2]) > 8
&& INTVAL (operands[2]) <= 16)
{
operands[2] = gen_rtx (CONST_INT, VOIDmode,
INTVAL (operands[2]) - 8);
operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
return \"addq%.w %#8,%0\;addq%.w %2,%0\";
}
if (INTVAL (operands[2]) < -8
&& INTVAL (operands[2]) >= -16)
{
operands[2] = gen_rtx (CONST_INT, VOIDmode,
- INTVAL (operands[2]) - 8);
operands[2] = GEN_INT (-INTVAL (operands[2]) - 8);
return \"subq%.w %#8,%0\;subq%.w %2,%0\";
}
}
@ -2321,8 +2314,7 @@
which could confuse us. */
if (INTVAL (operands[1]) >= 32768)
operands[1] = gen_rtx (CONST_INT, VOIDmode,
INTVAL (operands[1]) - 65536);
operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
if (INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= 8)
@ -2330,8 +2322,7 @@
if (INTVAL (operands[1]) < 0
&& INTVAL (operands[1]) >= -8)
{
operands[1] = gen_rtx (CONST_INT, VOIDmode,
- INTVAL (operands[1]));
operands[1] = GEN_INT (-INTVAL (operands[1]));
return \"subq%.w %1,%0\";
}
/* On the CPU32 it is faster to use two addqw instructions to
@ -2342,15 +2333,13 @@
if (INTVAL (operands[1]) > 8
&& INTVAL (operands[1]) <= 16)
{
operands[1] = gen_rtx (CONST_INT, VOIDmode,
INTVAL (operands[1]) - 8);
operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
return \"addq%.w %#8,%0\;addq%.w %1,%0\";
}
if (INTVAL (operands[1]) < -8
&& INTVAL (operands[1]) >= -16)
{
operands[1] = gen_rtx (CONST_INT, VOIDmode,
- INTVAL (operands[1]) - 8);
operands[1] = GEN_INT (-INTVAL (operands[1]) - 8);
return \"subq%.w %#8,%0\;subq%.w %1,%0\";
}
}
@ -2381,8 +2370,7 @@
which could confuse us. */
if (INTVAL (operands[1]) >= 32768)
operands[1] = gen_rtx (CONST_INT, VOIDmode,
INTVAL (operands[1]) - 65536);
operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
if (INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= 8)
@ -2390,8 +2378,7 @@
if (INTVAL (operands[1]) < 0
&& INTVAL (operands[1]) >= -8)
{
operands[1] = gen_rtx (CONST_INT, VOIDmode,
- INTVAL (operands[1]));
operands[1] = GEN_INT (-INTVAL (operands[1]));
return \"subq%.w %1,%0\";
}
/* On the CPU32 it is faster to use two addqw instructions to
@ -2402,15 +2389,13 @@
if (INTVAL (operands[1]) > 8
&& INTVAL (operands[1]) <= 16)
{
operands[1] = gen_rtx (CONST_INT, VOIDmode,
INTVAL (operands[1]) - 8);
operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
return \"addq%.w %#8,%0\;addq%.w %1,%0\";
}
if (INTVAL (operands[1]) < -8
&& INTVAL (operands[1]) >= -16)
{
operands[1] = gen_rtx (CONST_INT, VOIDmode,
- INTVAL (operands[1]) - 8);
operands[1] = GEN_INT (-INTVAL (operands[1]) - 8);
return \"subq%.w %#8,%0\;subq%.w %1,%0\";
}
}
@ -2436,15 +2421,14 @@
if (GET_CODE (operands[2]) == CONST_INT)
{
if (INTVAL (operands[2]) >= 128)
operands[2] = gen_rtx (CONST_INT, VOIDmode,
INTVAL (operands[2]) - 256);
operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
if (INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) <= 8)
return \"addq%.b %2,%0\";
if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
{
operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]));
operands[2] = GEN_INT (-INTVAL (operands[2]));
return \"subq%.b %2,%0\";
}
}
@ -2463,15 +2447,14 @@
if (GET_CODE (operands[1]) == CONST_INT)
{
if (INTVAL (operands[1]) >= 128)
operands[1] = gen_rtx (CONST_INT, VOIDmode,
INTVAL (operands[1]) - 256);
operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
if (INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= 8)
return \"addq%.b %1,%0\";
if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
{
operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
operands[1] = GEN_INT (-INTVAL (operands[1]));
return \"subq%.b %1,%0\";
}
}
@ -2490,15 +2473,14 @@
if (GET_CODE (operands[1]) == CONST_INT)
{
if (INTVAL (operands[1]) >= 128)
operands[1] = gen_rtx (CONST_INT, VOIDmode,
INTVAL (operands[1]) - 256);
operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
if (INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= 8)
return \"addq%.b %1,%0\";
if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
{
operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
operands[1] = gen_INT (-INTVAL (operands[1]));
return \"subq%.b %1,%0\";
}
}
@ -2648,7 +2630,7 @@
{
CC_STATUS_INIT;
if (GET_CODE (operands[1]) == REG)
operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else
operands[1] = adj_offsettable_operand (operands[1], 4);
return \"sub%.l %1,%0\";
@ -2674,7 +2656,7 @@
else
{
if (GET_CODE (operands[2]) == REG)
operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
operands[1] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
else if (GET_CODE (operands[2]) == CONST_DOUBLE)
{
operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
@ -2699,9 +2681,10 @@
CC_STATUS_INIT;
if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
{
operands[1] = gen_rtx (MEM, SImode,
gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
gen_rtx (CONST_INT, VOIDmode, -8)));
operands[1]
= gen_rtx_MEM (SImode,
gen_rtx_PLUS (VOIDmode, XEXP(operands[0], 0),
GEN_INT (-8)));
return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
}
else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
@ -3198,7 +3181,7 @@
&& floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
{
int i = floating_exact_log2 (operands[2]);
operands[2] = gen_rtx (CONST_INT, VOIDmode, i);
operands[2] = GEN_INT (i);
return \"fscale%.l %2,%0\";
}
if (REG_P (operands[2]))
@ -3552,7 +3535,7 @@
}
}
if (GET_CODE (operands[0]) == REG)
operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[0] = adj_offsettable_operand (operands[0], 4);
switch (INTVAL (lo))
@ -3702,7 +3685,7 @@
}
}
if (GET_CODE (operands[0]) == REG)
operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[0] = adj_offsettable_operand (operands[0], 4);
switch (INTVAL (lo))
@ -3898,7 +3881,7 @@
}
}
if (GET_CODE (operands[0]) == REG)
operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[0] = adj_offsettable_operand (operands[0], 4);
switch (INTVAL (lo))
@ -4026,7 +4009,7 @@
if (which_alternative == 0)
return \"neg%.l %0\;negx%.l %0\";
if (GET_CODE (operands[0]) == REG)
operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[1] = adj_offsettable_operand (operands[0], 4);
if (ADDRESS_REG_P (operands[0]))
@ -4041,7 +4024,7 @@
"TARGET_5200"
"*
{
operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
return \"neg%.l %1\;negx%.l %0\";
} ")
@ -4137,7 +4120,7 @@
{
if (DATA_REG_P (operands[0]))
{
operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
operands[1] = GEN_INT (31);
return \"bchg %1,%0\";
}
if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
@ -4193,7 +4176,7 @@
{
if (DATA_REG_P (operands[0]))
{
operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
operands[1] = GEN_INT (31);
return \"bchg %1,%0\";
}
if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
@ -4336,7 +4319,7 @@
{
CC_STATUS_INIT;
if (GET_CODE (operands[0]) == REG)
operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
|| GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
operands[1] = operands[0];
@ -4408,7 +4391,7 @@
{
CC_STATUS_INIT;
if (GET_CODE (operands[0]) == REG)
operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[2] = adj_offsettable_operand (operands[0], 4);
if (ADDRESS_REG_P (operands[0]))
@ -4453,11 +4436,11 @@
{
CC_STATUS_INIT;
if (GET_CODE (operands[1]) == REG)
operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else
operands[3] = adj_offsettable_operand (operands[1], 4);
if (GET_CODE (operands[0]) == REG)
operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
return \"clr%.l %0\;move%.l %3,%0\";
else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
@ -4480,7 +4463,7 @@
|| INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
"*
{
operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
if (INTVAL (operands[2]) == 1)
return \"add%.l %1,%1\;addx%.l %0,%0\";
else if (INTVAL (operands[2]) == 8)
@ -4535,7 +4518,7 @@
{
CC_STATUS_INIT;
operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
}")
@ -4601,7 +4584,7 @@
&& INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
"*
{
operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
}")
@ -4635,7 +4618,7 @@
"*
{
CC_STATUS_INIT;
operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
if (TARGET_68020)
return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
else
@ -4673,7 +4656,7 @@
|| INTVAL (operands[2]) == 63))"
"*
{
operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
if (INTVAL (operands[2]) == 63)
return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
CC_STATUS_INIT;
@ -4780,7 +4763,7 @@
;; "*
;;{
;; if (GET_CODE (operands[1]) == REG)
;; operands[2] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
;; else
;; operands[2] = adj_offsettable_operand (operands[1], 4);
;; return \"move%.l %0,%2\;clr%.l %1\";
@ -4809,11 +4792,11 @@
if (which_alternative == 2)
return \"clr%.l %0\;move%.l %1,%0\";
if (GET_CODE (operands[0]) == REG)
operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[2] = adj_offsettable_operand (operands[0], 4);
if (GET_CODE (operands[1]) == REG)
operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else
operands[3] = adj_offsettable_operand (operands[1], 4);
if (ADDRESS_REG_P (operands[0]))
@ -4833,7 +4816,7 @@
|| INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63))"
"*
{
operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
if (INTVAL (operands[2]) == 63)
return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
CC_STATUS_INIT;
@ -4900,7 +4883,7 @@
"*
{
/* I think lsr%.w sets the CC properly. */
operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
}")
@ -4952,7 +4935,7 @@
return \"swap %0\";
else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
{
operands[2] = gen_rtx (CONST_INT, VOIDmode, 32 - INTVAL (operands[2]));
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
return \"ror%.l %2,%0\";
}
else
@ -4968,7 +4951,7 @@
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
{
operands[2] = gen_rtx (CONST_INT, VOIDmode, 16 - INTVAL (operands[2]));
operands[2] = GEN_INT (16 - INTVAL (operands[2]));
return \"ror%.w %2,%0\";
}
else
@ -4984,7 +4967,7 @@
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
{
operands[2] = gen_rtx (CONST_INT, VOIDmode, 16 - INTVAL (operands[2]));
operands[2] = GEN_INT (16 - INTVAL (operands[2]));
return \"ror%.w %2,%0\";
}
else
@ -5000,7 +4983,7 @@
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
{
operands[2] = gen_rtx (CONST_INT, VOIDmode, 8 - INTVAL (operands[2]));
operands[2] = GEN_INT (8 - INTVAL (operands[2]));
return \"ror%.b %2,%0\";
}
else
@ -5016,7 +4999,7 @@
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
{
operands[2] = gen_rtx (CONST_INT, VOIDmode, 8 - INTVAL (operands[2]));
operands[2] = GEN_INT (8 - INTVAL (operands[2]));
return \"ror%.b %2,%0\";
}
else
@ -5472,8 +5455,7 @@
{
int width = GET_CODE (operands[0]) == REG ? 31 : 7;
return output_btst (operands,
gen_rtx (CONST_INT, VOIDmode,
width - INTVAL (operands[2])),
GEN_INT (width - INTVAL (operands[2])),
operands[0],
insn, 1000);
/* Pass 1000 as SIGNPOS argument so that btst will
@ -5500,8 +5482,7 @@
{
int width = GET_CODE (operands[0]) == REG ? 31 : 7;
return output_btst (operands,
gen_rtx (CONST_INT, VOIDmode,
width - INTVAL (operands[2])),
GEN_INT (width - INTVAL (operands[2])),
operands[0],
insn, 1000);
/* Pass 1000 as SIGNPOS argument so that btst will
@ -5845,7 +5826,7 @@
#endif
}
if (GET_CODE (operands[0]) == REG)
operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[3] = adj_offsettable_operand (operands[0], 4);
if (! ADDRESS_REG_P (operands[0]))
@ -5906,7 +5887,7 @@
}
CC_STATUS_INIT;
if (GET_CODE (operands[0]) == REG)
operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[3] = adj_offsettable_operand (operands[0], 4);
if (!ADDRESS_REG_P (operands[0]))
@ -6372,8 +6353,8 @@
"
{
#ifdef CASE_VECTOR_PC_RELATIVE
operands[0] = gen_rtx (PLUS, SImode, pc_rtx,
gen_rtx (SIGN_EXTEND, SImode, operands[0]));
operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
gen_rtx_SIGN_EXTEND (SImode, operands[0]));
#endif
}")
@ -6851,8 +6832,8 @@
"NEED_PROBE"
"*
{
operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx,
gen_rtx (CONST_INT, VOIDmode, NEED_PROBE));
operands[0] = gen_rtx_PLUS (SImode, stack_pointer_rtx,
GEN_INT (NEED_PROBE));
return \"tstl %a0\";
}")
@ -6864,7 +6845,7 @@
{
if (current_function_pops_args == 0)
return \"rts\";
operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args);
operands[0] = GEN_INT (current_function_pops_args);
return \"rtd %0\";
}")
@ -6928,7 +6909,7 @@
"*
{
rtx xoperands[2];
xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
output_asm_insn (\"move%.l %1,%@\", xoperands);
output_asm_insn (\"move%.l %1,%-\", operands);
return \"fmove%.d %+,%0\";
@ -6952,7 +6933,7 @@
{
rtx xoperands[2];
xoperands[0] = stack_pointer_rtx;
xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
#ifndef NO_ADDSUB_Q
if (INTVAL (xoperands[1]) <= 8)
{
@ -6963,8 +6944,7 @@
}
else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
{
xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
INTVAL (xoperands[1]) - 8);
xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
}
else
@ -7003,7 +6983,7 @@
{
rtx xoperands[2];
xoperands[0] = stack_pointer_rtx;
xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
#ifndef NO_ADDSUB_Q
if (INTVAL (xoperands[1]) <= 8)
{
@ -7014,8 +6994,7 @@
}
else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
{
xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
INTVAL (xoperands[1]) - 8);
xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
}
else
@ -7057,9 +7036,9 @@
xoperands[1] = operands[1];
xoperands[2]
= gen_rtx (MEM, QImode,
gen_rtx (PLUS, VOIDmode, stack_pointer_rtx,
gen_rtx (CONST_INT, VOIDmode, 3)));
= gen_rtx_MEM (QImode,
gen_rtx_PLUS (VOIDmode, stack_pointer_rtx,
GEN_INT (3)));
xoperands[3] = stack_pointer_rtx;
if (!TARGET_5200)
output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
@ -7404,7 +7383,7 @@
if (REG_P (operands[0]))
{
output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
return \"move%.l %+,%0\";
}
return \"fmove%.d %f1,%0\";