rs6000.md (ltu<mode>_compare): Convert to define_insn_and_split.
* config/rs6000/rs6000.md (ltu<mode>_compare): Convert to define_insn_and_split. (plus_ltu<mode>_compare): Same. (gtu<mode>_compare): Same. (plus_gtu<mode>_compare): Same. From-SVN: r103253
This commit is contained in:
David Edelsohn
parent
90ff949ff7
commit
1e24ce8318
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@ -1,7 +1,16 @@
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2005-08-18 David Edelsohn <edelsohn@gnu.org>
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* config/rs6000/rs6000.md (ltu<mode>_compare): Convert to
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define_insn_and_split.
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(plus_ltu<mode>_compare): Same.
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(gtu<mode>_compare): Same.
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(plus_gtu<mode>_compare): Same.
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2005-08-18 Dorit Nuzman <dorit@il.ibm.com>
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PR tree-optimization/22228
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* tree-ssa-loop (pass_vectorize): Add TODO_verify_loops to todo_flags_start.
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* tree-ssa-loop (pass_vectorize): Add TODO_verify_loops to
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todo_flags_start.
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* tree-vect-transform.c (vect_transform_loop): Mark the variables that
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are recorded in vect_vnames_to_rename for renaming.
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* tree-vectorizer.c (vect_vnames_to_rename): New global bitmap.
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@ -11995,7 +11995,7 @@
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(set (match_dup 0) (neg:P (match_dup 0)))]
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"")
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(define_insn "*ltu<mode>_compare"
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(define_insn_and_split "*ltu<mode>_compare"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC
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(ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
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@ -12004,35 +12004,19 @@
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(set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
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(ltu:P (match_dup 1) (match_dup 2)))]
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""
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"@
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{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
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{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
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#
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#"
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[(set_attr "type" "compare")
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(set_attr "length" "12,12,16,16")])
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(define_split
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[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
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(compare:CC
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(ltu:P (match_operand:P 1 "gpc_reg_operand" "")
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(match_operand:P 2 "reg_or_neg_short_operand" ""))
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(const_int 0)))
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(set (match_operand:P 0 "gpc_reg_operand" "")
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(ltu:P (match_dup 1) (match_dup 2)))]
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"reload_completed"
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[(set (match_dup 0)
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(ltu:P (match_dup 1) (match_dup 2)))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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"#"
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""
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[(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
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(parallel [(set (match_dup 3)
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(compare:CC (neg:P (match_dup 0)) (const_int 0)))
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(set (match_dup 0) (neg:P (match_dup 0)))])]
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"")
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(define_insn_and_split "*plus_ltu<mode>"
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[(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
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(plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
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(match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
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(match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
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(match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
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""
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"#"
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"&& !reg_overlap_mentioned_p (operands[0], operands[3])"
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@ -12040,73 +12024,23 @@
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(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
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"")
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(define_insn ""
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC
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(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
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(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
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(const_int 0)))
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(clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
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"TARGET_32BIT"
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"@
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{sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
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{ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
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#
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#"
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[(set_attr "type" "compare")
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(set_attr "length" "12,12,16,16")])
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(define_split
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[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
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(compare:CC
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(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_neg_short_operand" ""))
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(match_operand:SI 3 "gpc_reg_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 4 ""))]
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 4)
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(plus:SI (ltu:SI (match_dup 1) (match_dup 2))
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(match_dup 3)))
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(set (match_dup 0)
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(compare:CC (match_dup 4)
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(const_int 0)))]
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"")
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(define_insn ""
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(define_insn_and_split "*plus_ltu<mode>_compare"
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC
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(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
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(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
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(plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
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(match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
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(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"TARGET_32BIT"
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"@
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{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
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{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
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#
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#"
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[(set_attr "type" "compare")
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(set_attr "length" "12,12,16,16")])
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(define_split
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[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
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(compare:CC
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(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_neg_short_operand" ""))
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(match_operand:SI 3 "gpc_reg_operand" ""))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 0)
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(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(set (match_dup 4)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
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(plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
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""
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"#"
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"&& !reg_overlap_mentioned_p (operands[0], operands[3])"
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[(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
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(parallel [(set (match_dup 4)
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(compare:CC (minus:P (match_dup 3) (match_dup 0))
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(const_int 0)))
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(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
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"")
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(define_insn "*neg_ltu<mode>"
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@ -12799,7 +12733,7 @@
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(const_int 0)))]
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"")
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(define_insn ""
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(define_insn "*neg_gt0si"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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(const_int 0))))]
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@ -12808,7 +12742,7 @@
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[(set_attr "type" "three")
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(set_attr "length" "12")])
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(define_insn ""
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(define_insn "neg_gt0di"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
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(neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
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(const_int 0))))]
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@ -12836,7 +12770,7 @@
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(set (match_dup 0) (neg:P (match_dup 0)))]
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"")
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(define_insn "*gtu<mode>_compare"
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(define_insn_and_split "*gtu<mode>_compare"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC
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(gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
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@ -12845,29 +12779,15 @@
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(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
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(gtu:P (match_dup 1) (match_dup 2)))]
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""
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"@
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{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
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#"
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[(set_attr "type" "compare")
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(set_attr "length" "12,16")])
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(define_split
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[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
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(compare:CC
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(gtu:P (match_operand:P 1 "gpc_reg_operand" "")
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(match_operand:P 2 "reg_or_short_operand" ""))
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(const_int 0)))
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(set (match_operand:P 0 "gpc_reg_operand" "")
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(gtu:P (match_dup 1) (match_dup 2)))]
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"reload_completed"
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[(set (match_dup 0)
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(gtu:P (match_dup 1) (match_dup 2)))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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"#"
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""
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[(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
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(parallel [(set (match_dup 3)
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(compare:CC (neg:P (match_dup 0)) (const_int 0)))
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(set (match_dup 0) (neg:P (match_dup 0)))])]
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"")
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(define_insn_and_split "plus_gtu<mode>"
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(define_insn_and_split "*plus_gtu<mode>"
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[(set (match_operand:P 0 "gpc_reg_operand" "=&r")
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(plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
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(match_operand:P 2 "reg_or_short_operand" "rI"))
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@ -12879,142 +12799,23 @@
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(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
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"")
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(define_insn ""
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC
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(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
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(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
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(const_int 0)))
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(clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
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"TARGET_32BIT"
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"@
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{ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
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{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
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#
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#"
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[(set_attr "type" "compare")
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(set_attr "length" "8,12,12,16")])
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(define_split
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[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
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(compare:CC
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(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_short_operand" ""))
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(match_operand:SI 3 "gpc_reg_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 4 ""))]
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 4)
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(plus:SI (gtu:SI (match_dup 1) (match_dup 2))
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(match_dup 3)))
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(set (match_dup 0)
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(compare:CC (match_dup 4)
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(const_int 0)))]
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"")
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(define_insn ""
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC
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(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
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(match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
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(const_int 0)))
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(clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
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"TARGET_64BIT"
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"@
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addic %4,%1,%k2\;addze. %4,%3
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subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3
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#
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#"
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[(set_attr "type" "compare")
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(set_attr "length" "8,12,12,16")])
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(define_split
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[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
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(compare:CC
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(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
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(match_operand:DI 2 "reg_or_short_operand" ""))
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(match_operand:DI 3 "gpc_reg_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:DI 4 ""))]
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"TARGET_64BIT && reload_completed"
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[(set (match_dup 4)
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(plus:DI (gtu:DI (match_dup 1) (match_dup 2))
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(match_dup 3)))
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(set (match_dup 0)
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(compare:CC (match_dup 4)
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(const_int 0)))]
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"")
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(define_insn ""
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(define_insn_and_split "*plus_gtu<mode>_compare"
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC
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(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
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(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
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(plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
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(match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
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(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"TARGET_32BIT"
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"@
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{ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
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{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
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#
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#"
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[(set_attr "type" "compare")
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(set_attr "length" "8,12,12,16")])
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(define_split
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[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
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(compare:CC
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(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_short_operand" ""))
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(match_operand:SI 3 "gpc_reg_operand" ""))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 0)
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(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(set (match_dup 4)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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"")
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(define_insn ""
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC
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(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
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(match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
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(const_int 0)))
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(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
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(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"TARGET_64BIT"
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"@
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addic %0,%1,%k2\;addze. %0,%3
|
||||
subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3
|
||||
#
|
||||
#"
|
||||
[(set_attr "type" "compare")
|
||||
(set_attr "length" "8,12,12,16")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC
|
||||
(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:DI 2 "reg_or_short_operand" ""))
|
||||
(match_operand:DI 3 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"TARGET_64BIT && reload_completed"
|
||||
[(set (match_dup 0)
|
||||
(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(set (match_dup 4)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
|
||||
(plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
""
|
||||
"#"
|
||||
"&& !reg_overlap_mentioned_p (operands[0], operands[3])"
|
||||
[(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
|
||||
(parallel [(set (match_dup 4)
|
||||
(compare:CC (minus:P (match_dup 3) (match_dup 0))
|
||||
(const_int 0)))
|
||||
(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
|
||||
"")
|
||||
|
||||
(define_insn "*neg_gtu<mode>"
|
||||
|
|
|
|||
Loading…
Reference in New Issue