[arm] Introduce arm_carry_operation
An earlier patch introduced arm_borrow_operation, this one introduces the carry variant, which is the same except that the logic of the carry-setting is inverted. Having done this we can now match more cases where the carry flag is propagated from comparisons with different modes without having to define even more patterns. A few small changes to the expand patterns are required to directly create the carry representation. The iterators LTUGEU is no-longer needed and removed, as is the code attribute 'cnb'. Finally, we fix a long-standing bug which was probably inert before: in Thumb2 a shift with ADC can only be by an immediate amount; register-specified shifts are not permitted. * config/arm/predicates.md (arm_carry_operation): New special predicate. * config/arm/iterators.md (LTUGEU): Delete iterator. (cnb): Delete code attribute. (optab): Delete ltu and geu elements. * config/arm/arm.md (addsi3_carryin): Renamed from addsi3_carryin_<optab>. Remove iterator and use arm_carry_operand. (add0si3_carryin): Similarly, but from add0si3_carryin_<optab>. (addsi3_carryin_alt2): Similarly, but from addsi3_carryin_alt2_<optab>. (addsi3_carryin_clobercc): Similarly. (addsi3_carryin_shift): Similarly. Do not allow register shifts in Thumb2 state. From-SVN: r277171
This commit is contained in:
Richard Earnshaw
Richard Earnshaw
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bc8dd50fe4
commit
1e271beeec
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@ -1,3 +1,18 @@
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2019-10-18 Richard Earnshaw <rearnsha@arm.com>
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* config/arm/predicates.md (arm_carry_operation): New special
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predicate.
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* config/arm/iterators.md (LTUGEU): Delete iterator.
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(cnb): Delete code attribute.
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(optab): Delete ltu and geu elements.
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* config/arm/arm.md (addsi3_carryin): Renamed from
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addsi3_carryin_<optab>. Remove iterator and use arm_carry_operand.
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(add0si3_carryin): Similarly, but from add0si3_carryin_<optab>.
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(addsi3_carryin_alt2): Similarly, but from addsi3_carryin_alt2_<optab>.
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(addsi3_carryin_clobercc): Similarly.
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(addsi3_carryin_shift): Similarly. Do not allow register shifts in
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Thumb2 state.
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2019-10-18 Richard Earnshaw <rearnsha@arm.com>
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* config/arm/arm.md (arm_subdi3): Delete insn.
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@ -471,10 +471,12 @@
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hi_op2 = force_reg (SImode, hi_op2);
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emit_insn (gen_addsi3_compareC (lo_dest, lo_op1, lo_op2));
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rtx carry = gen_rtx_LTU (SImode, gen_rtx_REG (CC_Cmode, CC_REGNUM),
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const0_rtx);
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if (hi_op2 == const0_rtx)
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emit_insn (gen_add0si3_carryin_ltu (hi_dest, hi_op1));
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emit_insn (gen_add0si3_carryin (hi_dest, hi_op1, carry));
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else
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emit_insn (gen_addsi3_carryin_ltu (hi_dest, hi_op1, hi_op2));
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emit_insn (gen_addsi3_carryin (hi_dest, hi_op1, hi_op2, carry));
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}
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if (lo_result != lo_dest)
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@ -858,11 +860,11 @@
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(set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_imm,alus_sreg")]
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)
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(define_insn "addsi3_carryin_<optab>"
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(define_insn "addsi3_carryin"
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[(set (match_operand:SI 0 "s_register_operand" "=l,r,r")
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(plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%l,r,r")
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(match_operand:SI 2 "arm_not_operand" "0,rI,K"))
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(LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
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(match_operand:SI 3 "arm_carry_operation" "")))]
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"TARGET_32BIT"
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"@
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adc%?\\t%0, %1, %2
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@ -877,9 +879,9 @@
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)
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;; Canonicalization of the above when the immediate is zero.
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(define_insn "add0si3_carryin_<optab>"
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(define_insn "add0si3_carryin"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))
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(plus:SI (match_operand:SI 2 "arm_carry_operation" "")
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(match_operand:SI 1 "arm_not_operand" "r")))]
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"TARGET_32BIT"
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"adc%?\\t%0, %1, #0"
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@ -889,9 +891,9 @@
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(set_attr "type" "adc_imm")]
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)
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(define_insn "*addsi3_carryin_alt2_<optab>"
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(define_insn "*addsi3_carryin_alt2"
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[(set (match_operand:SI 0 "s_register_operand" "=l,r,r")
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(plus:SI (plus:SI (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))
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(plus:SI (plus:SI (match_operand:SI 3 "arm_carry_operation" "")
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(match_operand:SI 1 "s_register_operand" "%l,r,r"))
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(match_operand:SI 2 "arm_not_operand" "l,rI,K")))]
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"TARGET_32BIT"
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@ -907,28 +909,30 @@
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(set_attr "type" "adc_reg,adc_reg,adc_imm")]
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)
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(define_insn "*addsi3_carryin_shift_<optab>"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(define_insn "*addsi3_carryin_shift"
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[(set (match_operand:SI 0 "s_register_operand" "=r,r")
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(plus:SI (plus:SI
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(match_operator:SI 2 "shift_operator"
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[(match_operand:SI 3 "s_register_operand" "r")
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(match_operand:SI 4 "reg_or_int_operand" "rM")])
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(LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0)))
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(match_operand:SI 1 "s_register_operand" "r")))]
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[(match_operand:SI 3 "s_register_operand" "r,r")
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(match_operand:SI 4 "shift_amount_operand" "M,r")])
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(match_operand:SI 5 "arm_carry_operation" ""))
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(match_operand:SI 1 "s_register_operand" "r,r")))]
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"TARGET_32BIT"
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"adc%?\\t%0, %1, %3%S2"
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[(set_attr "conds" "use")
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(set_attr "arch" "32,a")
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(set_attr "shift" "3")
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(set_attr "predicable" "yes")
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(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
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(const_string "alu_shift_imm")
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(const_string "alu_shift_reg")))]
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)
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(define_insn "*addsi3_carryin_clobercc_<optab>"
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(define_insn "*addsi3_carryin_clobercc"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r")
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(match_operand:SI 2 "arm_rhs_operand" "rI"))
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(LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))
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(match_operand:SI 3 "arm_carry_operation" "")))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_32BIT"
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"adcs%?\\t%0, %1, %2"
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@ -219,11 +219,6 @@
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;; Code iterators
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;;----------------------------------------------------------------------------
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;; A list of condition codes used in compare instructions where
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;; the carry flag from the addition is used instead of doing the
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;; compare a second time.
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(define_code_iterator LTUGEU [ltu geu])
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;; The signed gt, ge comparisons
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(define_code_iterator GTGE [gt ge])
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@ -809,13 +804,9 @@
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(define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u")
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(umax "u")])
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(define_code_attr cnb [(ltu "CC_C") (geu "CC")])
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;; Map rtl operator codes to optab names
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(define_code_attr optab
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[(ltu "ltu")
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(geu "geu")
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(and "and")
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[(and "and")
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(ior "ior")
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(xor "xor")])
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@ -356,6 +356,27 @@
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(define_special_predicate "lt_ge_comparison_operator"
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(match_code "lt,ge"))
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(define_special_predicate "arm_carry_operation"
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(match_code "geu,ltu")
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{
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if (XEXP (op, 1) != const0_rtx)
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return false;
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rtx op0 = XEXP (op, 0);
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if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
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return false;
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machine_mode ccmode = GET_MODE (op0);
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if (ccmode == CC_Cmode)
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return GET_CODE (op) == LTU;
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else if (ccmode == CCmode || ccmode == CC_RSBmode)
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return GET_CODE (op) == GEU;
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return false;
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}
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)
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;; Match a "borrow" operation for use with SBC. The precise code will
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;; depend on the form of the comparison. This is generally the inverse of
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;; a carry operation, since the logic of SBC uses "not borrow" in it's
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