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re PR target/38598 (MIPS extendsidi2 does not have a LO alternative)

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gcc/
	PR target/38598
	* config/mips/mips.md (extendsidi2): Add an "l" alternative.
	Update commentary.

gcc/testsuite/
	PR target/38598
	* gcc.target/mips/madd-7.c: Remove -mlong32.
	* gcc.target/mips/msub-7.c: Likewise.

From-SVN: r171572
This commit is contained in:
Richard Sandiford 2011-03-27 09:33:20 +00:00 committed by Richard Sandiford
parent b99ce2a8b9
commit 1ea9206ac5
5 changed files with 30 additions and 14 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2011-03-27 Richard Sandiford <rdsandiford@googlemail.com>
PR target/38598
* config/mips/mips.md (extendsidi2): Add an "l" alternative.
Update commentary.
2011-03-27 Richard Sandiford <rdsandiford@googlemail.com>
* config/mips/mips.c (mips_prepare_builtin_arg): Replace icode and

26
gcc/config/mips/mips.md
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@ -2963,19 +2963,25 @@
;; Extension insns.
;; Those for integer source operand are ordered widest source type first.
;; When TARGET_64BIT, all SImode integer registers should already be in
;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
;; therefore get rid of register->register instructions if we constrain
;; the source to be in the same register as the destination.
;; When TARGET_64BIT, all SImode integer and accumulator registers
;; should already be in sign-extended form (see TRULY_NOOP_TRUNCATION
;; and truncdisi2). We can therefore get rid of register->register
;; instructions if we constrain the source to be in the same register as
;; the destination.
;;
;; The register alternative has type "arith" so that the pre-reload
;; scheduler will treat it as a move. This reflects what happens if
;; the register alternative needs a reload.
;; Only the pre-reload scheduler sees the type of the register alternatives;
;; we split them into nothing before the post-reload scheduler runs.
;; These alternatives therefore have type "move" in order to reflect
;; what happens if the two pre-reload operands cannot be tied, and are
;; instead allocated two separate GPRs. We don't distinguish between
;; the GPR and LO cases because we don't usually know during pre-reload
;; scheduling whether an operand will be LO or not.
(define_insn_and_split "extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
[(set (match_operand:DI 0 "register_operand" "=d,l,d")
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,0,m")))]
"TARGET_64BIT"
"@
#
#
lw\t%0,%1"
"&& reload_completed && register_operand (operands[1], VOIDmode)"
@ -2984,7 +2990,7 @@
emit_note (NOTE_INSN_DELETED);
DONE;
}
[(set_attr "move_type" "move,load")
[(set_attr "move_type" "move,move,load")
(set_attr "mode" "DI")])
(define_expand "extend<SHORT:mode><GPR:mode>2"

6
gcc/testsuite/ChangeLog
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@ -1,3 +1,9 @@
2011-03-27 Richard Sandiford <rdsandiford@googlemail.com>
PR target/38598
* gcc.target/mips/madd-7.c: Remove -mlong32.
* gcc.target/mips/msub-7.c: Likewise.
2011-03-27 Ira Rosen <ira.rosen@linaro.org>
* gcc.dg/vect/vect-outer-5.c: Reduce the distance between data

3
gcc/testsuite/gcc.target/mips/madd-7.c
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@ -1,5 +1,4 @@
/* -mlong32 added because of PR target/38598. */
/* { dg-options "-O2 -march=5kc -mlong32" } */
/* { dg-options "-O2 -march=5kc" } */
/* { dg-final { scan-assembler-not "\tmul\t" } } */
/* { dg-final { scan-assembler "\tmadd\t" } } */

3
gcc/testsuite/gcc.target/mips/msub-7.c
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@ -1,5 +1,4 @@
/* -mlong32 added because of PR target/38598. */
/* { dg-options "-O2 -march=5kc -mlong32" } */
/* { dg-options "-O2 -march=5kc" } */
/* { dg-final { scan-assembler-not "\tmul\t" } } */
/* { dg-final { scan-assembler "\tmsub\t" } } */