i386.c (x86_cmpxchg, x86_xadd): New.
* config/i386/i386.c (x86_cmpxchg, x86_xadd): New.
(ix86_compare_emitted): New.
(ix86_expand_compare): Use ix86_compare_emitted if set.
(ix86_expand_setcc): Only emit REG_EQUAL if both ix86_compare_op0
and ix86_compare_op0 are set.
* config/i386/i386.h (x86_cmpxchg, x86_xadd): Declare.
(TARGET_CMPXCHG, TARGET_XADD): New.
(ix86_compare_emitted): Declare.
* config/i386/i386.md: Include sync.md
(UNSPECV_CMPXCHG_1, UNSPECV_CMPXCHG_2): New.
(UNSPECV_XCHG, UNSPECV_LOCK): New.
* config/i386/sync.md: New file.
From-SVN: r98155
This commit is contained in:
Richard Henderson
Richard Henderson
parent
48ae6c138c
commit
1ef45b7773
@ -1,3 +1,18 @@
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2004-04-14 Richard Henderson <rth@redhat.com>
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* config/i386/i386.c (x86_cmpxchg, x86_xadd): New.
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(ix86_compare_emitted): New.
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(ix86_expand_compare): Use ix86_compare_emitted if set.
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(ix86_expand_setcc): Only emit REG_EQUAL if both ix86_compare_op0
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and ix86_compare_op0 are set.
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* config/i386/i386.h (x86_cmpxchg, x86_xadd): Declare.
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(TARGET_CMPXCHG, TARGET_XADD): New.
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(ix86_compare_emitted): Declare.
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* config/i386/i386.md: Include sync.md
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(UNSPECV_CMPXCHG_1, UNSPECV_CMPXCHG_2): New.
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(UNSPECV_XCHG, UNSPECV_LOCK): New.
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* config/i386/sync.md: New file.
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2004-04-14 Richard Henderson <rth@redhat.com>
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PR middle-end/14311
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@ -584,6 +584,10 @@ const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_NOCONA | m_PPR
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const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
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const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6 | m_PENT;
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const int x86_use_bt = m_ATHLON_K8;
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/* Compare and exchange was added for 80486. */
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const int x86_cmpxchg = ~m_386;
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/* Exchange and add was added for 80486. */
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const int x86_xadd = ~m_386;
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/* In case the average insn count for single function invocation is
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lower than this constant, emit fast (but longer) prologue and
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@ -727,6 +731,7 @@ int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
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rtx ix86_compare_op0 = NULL_RTX;
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rtx ix86_compare_op1 = NULL_RTX;
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rtx ix86_compare_emitted = NULL_RTX;
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#define MAX_386_STACK_LOCALS 3
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/* Size of the register save area. */
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@ -9049,7 +9054,12 @@ ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
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if (bypass_test)
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*bypass_test = NULL_RTX;
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if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_FLOAT)
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if (ix86_compare_emitted)
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{
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ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
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ix86_compare_emitted = NULL_RTX;
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}
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else if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_FLOAT)
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ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
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second_test, bypass_test);
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else
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@ -9378,10 +9388,13 @@ ix86_expand_setcc (enum rtx_code code, rtx dest)
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}
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/* Attach a REG_EQUAL note describing the comparison result. */
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equiv = simplify_gen_relational (code, QImode,
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GET_MODE (ix86_compare_op0),
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ix86_compare_op0, ix86_compare_op1);
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set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
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if (ix86_compare_op0 && ix86_compare_op1)
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{
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equiv = simplify_gen_relational (code, QImode,
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GET_MODE (ix86_compare_op0),
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ix86_compare_op0, ix86_compare_op1);
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set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
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}
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return 1; /* DONE */
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}
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@ -253,6 +253,7 @@ extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
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extern const int x86_use_ffreep;
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extern const int x86_inter_unit_moves, x86_schedule;
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extern const int x86_use_bt;
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extern const int x86_cmpxchg, x86_xadd;
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extern int x86_prefetch_sse;
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#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
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@ -333,6 +334,9 @@ extern int x86_prefetch_sse;
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#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
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#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
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#define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch))
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#define TARGET_XADD (x86_xadd & (1 << ix86_arch))
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/* WARNING: Do not mark empty strings for translation, as calling
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gettext on an empty string does NOT return an empty
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string. */
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@ -2463,6 +2467,7 @@ extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
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extern rtx ix86_compare_op0; /* operand 0 for comparisons */
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extern rtx ix86_compare_op1; /* operand 1 for comparisons */
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extern rtx ix86_compare_emitted;
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/* To properly truncate FP values into integers, we need to set i387 control
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word. We can't emit proper mode switching code before reload, as spills
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@ -151,6 +151,10 @@
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(UNSPECV_ALIGN 7)
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(UNSPECV_MONITOR 8)
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(UNSPECV_MWAIT 9)
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(UNSPECV_CMPXCHG_1 10)
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(UNSPECV_CMPXCHG_2 11)
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(UNSPECV_XCHG 12)
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(UNSPECV_LOCK 13)
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])
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;; Registers by name.
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@ -19757,3 +19761,4 @@
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(include "sse.md")
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(include "mmx.md")
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(include "sync.md")
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158
gcc/config/i386/sync.md
Normal file
158
gcc/config/i386/sync.md
Normal file
@ -0,0 +1,158 @@
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;; GCC machine description for i386 synchronization instructions.
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;; Copyright (C) 2005
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;; Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 2, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING. If not, write to
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;; the Free Software Foundation, 59 Temple Place - Suite 330,
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;; Boston, MA 02111-1307, USA.
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(define_mode_macro IMODE [QI HI SI (DI "TARGET_64BIT")])
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(define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
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(define_mode_attr modeconstraint [(QI "q") (HI "r") (SI "r") (DI "r")])
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(define_mode_attr immconstraint [(QI "i") (HI "i") (SI "i") (DI "e")])
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;; ??? It would be possible to use cmpxchg8b on pentium for DImode
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;; changes. It's complicated because the insn uses ecx:ebx as the
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;; new value; note that the registers are reversed from the order
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;; that they'd be in with (reg:DI 2 ecx). Similarly for TImode
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;; data in 64-bit mode.
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(define_insn "sync_compare_and_swap<mode>"
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[(set (match_operand:IMODE 0 "register_operand" "=a")
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(unspec_volatile:IMODE
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[(match_operand:IMODE 1 "memory_operand" "+m")
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(match_operand:IMODE 2 "register_operand" "a")
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(match_operand:IMODE 3 "register_operand" "<modeconstraint>")]
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UNSPECV_CMPXCHG_1))
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(set (match_dup 1)
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(unspec_volatile:IMODE
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[(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG_2))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_CMPXCHG"
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"lock\;cmpxchg{<modesuffix>}\t{%3, %1|%1, %3}")
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(define_expand "sync_compare_and_swap_cc<mode>"
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[(parallel
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[(set (match_operand:IMODE 0 "register_operand" "")
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(unspec_volatile:IMODE
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[(match_operand:IMODE 1 "memory_operand" "")
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(match_operand:IMODE 2 "register_operand" "")
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(match_operand:IMODE 3 "register_operand" "")]
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UNSPECV_CMPXCHG_1))
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(set (match_dup 1)
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(unspec_volatile:IMODE
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[(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG_2))
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(set (match_dup 4)
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(compare:CCZ
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(unspec_volatile:IMODE
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[(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG_1)
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(match_dup 3)))])]
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"TARGET_CMPXCHG"
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{
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operands[4] = gen_rtx_REG (CCZmode, FLAGS_REG);
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ix86_compare_op0 = operands[3];
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ix86_compare_op1 = NULL;
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ix86_compare_emitted = operands[4];
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})
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(define_insn "*sync_compare_and_swap_cc<mode>"
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[(set (match_operand:IMODE 0 "register_operand" "=a")
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(unspec_volatile:IMODE
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[(match_operand:IMODE 1 "memory_operand" "+m")
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(match_operand:IMODE 2 "register_operand" "a")
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(match_operand:IMODE 3 "register_operand" "<modeconstraint>")]
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UNSPECV_CMPXCHG_1))
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(set (match_dup 1)
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(unspec_volatile:IMODE
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[(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG_2))
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(set (reg:CCZ FLAGS_REG)
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(compare:CCZ
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(unspec_volatile:IMODE
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[(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG_1)
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(match_dup 3)))]
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"TARGET_CMPXCHG"
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"lock\;cmpxchg{<modesuffix>}\t{%3, %1|%1, %3}")
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(define_insn "sync_old_add<mode>"
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[(set (match_operand:IMODE 0 "register_operand" "=<modeconstraint>")
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(unspec_volatile:IMODE
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[(match_operand:IMODE 1 "memory_operand" "+m")] UNSPECV_XCHG))
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(set (match_dup 1)
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(plus:IMODE (match_dup 1)
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(match_operand:IMODE 2 "register_operand" "0")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_XADD"
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"lock\;xadd{<modesuffix>}\t{%0, %1|%1, %0}")
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;; Recall that xchg implicitly sets LOCK#, so adding it again wastes space.
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(define_insn "sync_lock_test_and_set<mode>"
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[(set (match_operand:IMODE 0 "register_operand" "=<modeconstraint>")
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(unspec_volatile:IMODE
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[(match_operand:IMODE 1 "memory_operand" "+m")] UNSPECV_XCHG))
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(set (match_dup 1)
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(match_operand:IMODE 2 "register_operand" "0"))]
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""
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"xchg{<modesuffix>}\t{%1, %0|%0, %1}")
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(define_insn "sync_add<mode>"
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[(set (match_operand:IMODE 0 "memory_operand" "=m")
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(unspec_volatile:IMODE
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[(plus:IMODE (match_dup 0)
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(match_operand:IMODE 1 "nonmemory_operand" "r<immconstraint>"))]
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UNSPECV_LOCK))
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(clobber (reg:CC FLAGS_REG))]
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""
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"lock\;add{<modesuffix>}\t{%1, %0|%0, %1}")
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(define_insn "sync_sub<mode>"
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[(set (match_operand:IMODE 0 "memory_operand" "=m")
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(unspec_volatile:IMODE
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[(minus:IMODE (match_dup 0)
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(match_operand:IMODE 1 "nonmemory_operand" "r<immconstraint>"))]
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UNSPECV_LOCK))
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(clobber (reg:CC FLAGS_REG))]
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""
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"lock\;sub{<modesuffix>}\t{%1, %0|%0, %1}")
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(define_insn "sync_ior<mode>"
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[(set (match_operand:IMODE 0 "memory_operand" "=m")
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(unspec_volatile:IMODE
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[(ior:IMODE (match_dup 0)
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(match_operand:IMODE 1 "nonmemory_operand" "r<immconstraint>"))]
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UNSPECV_LOCK))
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(clobber (reg:CC FLAGS_REG))]
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""
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"lock\;or{<modesuffix>}\t{%1, %0|%0, %1}")
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(define_insn "sync_and<mode>"
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[(set (match_operand:IMODE 0 "memory_operand" "=m")
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(unspec_volatile:IMODE
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[(and:IMODE (match_dup 0)
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(match_operand:IMODE 1 "nonmemory_operand" "r<immconstraint>"))]
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UNSPECV_LOCK))
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(clobber (reg:CC FLAGS_REG))]
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""
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"lock\;and{<modesuffix>}\t{%1, %0|%0, %1}")
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(define_insn "sync_xor<mode>"
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[(set (match_operand:IMODE 0 "memory_operand" "=m")
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(unspec_volatile:IMODE
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[(xor:IMODE (match_dup 0)
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(match_operand:IMODE 1 "nonmemory_operand" "r<immconstraint>"))]
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UNSPECV_LOCK))
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(clobber (reg:CC FLAGS_REG))]
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""
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"lock\;xor{<modesuffix>}\t{%1, %0|%0, %1}")
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