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Do not enable -mblock-ops-vector-pair. 

Testing has shown that using the load vector pair and store vector pair
instructions for block moves has some performance issues on power10.

A patch on June 11th modified the code so that GCC would not set
-mblock-ops-vector-pair by default if we are tuning for power10, but it would
set the option if we were tuning for a different machine and have load and store
vector pair instructions enabled.

This patch eliminates the code setting -mblock-ops-vector-pair.  If you want to
generate load vector pair and store vector pair instructions for block moves,
you must use -mblock-ops-vector-pair.

2022-08-08   Michael Meissner  <meissner@linux.ibm.com>

gcc/

	* config/rs6000/rs6000.c (rs6000_option_override_internal): Remove code
	setting -mblock-ops-vector-pair.  Patch back ported from trunk, August
	3rd, 2022.
This commit is contained in:
Michael Meissner 2022-08-08 12:37:06 -04:00
parent 8356ccd0a4
commit 203152ef1f
1 changed files with 0 additions and 11 deletions
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11
gcc/config/rs6000/rs6000.c
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@ -4147,17 +4147,6 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_BLOCK_OPS_UNALIGNED_VSX;
}
if (!(rs6000_isa_flags_explicit & OPTION_MASK_BLOCK_OPS_VECTOR_PAIR))
{
/* Do not generate lxvp and stxvp on power10 since there are some
performance issues. */
if (TARGET_MMA && TARGET_EFFICIENT_UNALIGNED_VSX
&& rs6000_tune != PROCESSOR_POWER10)
rs6000_isa_flags |= OPTION_MASK_BLOCK_OPS_VECTOR_PAIR;
else
rs6000_isa_flags &= ~OPTION_MASK_BLOCK_OPS_VECTOR_PAIR;
}
/* Use long double size to select the appropriate long double. We use
TYPE_PRECISION to differentiate the 3 different long double types. We map
128 into the precision used for TFmode. */