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[Arm] Add 16-bit thumb alternatives to iorsi3_compare0[_scratch] 

The iorsi3_compare0 and iorsi3_compare0_scratch patterns can make use
of the 16-bit thumb orrs instruction if suitable registers are
allocated.  This patch adds the alternative to allow this to happen.

	* config/arm/arm.md (iorsi3_compare0): Add alternative for 16-bit thumb
	insn.
	(iorsi3_compare0_scratch): Likewise.

From-SVN: r274822
This commit is contained in:
Richard Earnshaw 2019-08-22 14:40:52 +00:00 committed by Richard Earnshaw
parent 391625888d
commit 203ef022c6
2 changed files with 22 additions and 10 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2019-08-22 Richard Earnshaw <rearnsha@arm.com>
* config/arm/arm.md (iorsi3_compare0): Add alternative for 16-bit thumb
insn.
(iorsi3_compare0_scratch): Likewise.
2019-08-22 Sylvia Taylor <sylvia.taylor@arm.com>
* config/aarch64/aarch64-simd-builtins.def:

26
gcc/config/arm/arm.md
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@ -3339,27 +3339,33 @@
(define_insn "*iorsi3_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r")
(match_operand:SI 2 "arm_rhs_operand" "I,r"))
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r,r")
(compare:CC_NOOV
(ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r")
(match_operand:SI 2 "arm_rhs_operand" "I,l,r"))
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
(ior:SI (match_dup 1) (match_dup 2)))]
"TARGET_32BIT"
"orrs%?\\t%0, %1, %2"
[(set_attr "conds" "set")
(set_attr "type" "logics_imm,logics_reg")]
(set_attr "arch" "*,t2,*")
(set_attr "length" "4,2,4")
(set_attr "type" "logics_imm,logics_reg,logics_reg")]
)
(define_insn "*iorsi3_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r")
(match_operand:SI 2 "arm_rhs_operand" "I,r"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r,r"))]
(compare:CC_NOOV
(ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r")
(match_operand:SI 2 "arm_rhs_operand" "I,l,r"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r,l,r"))]
"TARGET_32BIT"
"orrs%?\\t%0, %1, %2"
[(set_attr "conds" "set")
(set_attr "type" "logics_imm,logics_reg")]
(set_attr "arch" "*,t2,*")
(set_attr "length" "4,2,4")
(set_attr "type" "logics_imm,logics_reg,logics_reg")]
)
(define_expand "xordi3"