arm.c (arm_override_options): Use arm_ld_sched rather than testing a bit in tune_flags.
* arm.c (arm_override_options): Use arm_ld_sched rather than testing a bit in tune_flags. (const_double_needs_minipool): Likewise. Split most of the code out into ... (arm_const_double_inline_cost): ... new function here. * arm-protos.h (arm_const_double_inline_cost): Add prototype. * arm.h (EXTRA_CONSTRAINT_STR_ARM): Add D[abc] constraints for double- word constants of length 2, 3 and 4 insns respectively. (CONSTRAINT_LEN): The 'D' prefix is a 2-letter constraint. * arm.md (arm_movdi, movdf_soft_insn): Add alternatives for D[abc] constraints. Set insn lenghts accordingly. From-SVN: r90962
This commit is contained in:
Richard Earnshaw
Richard Earnshaw
parent
9eaf7da094
commit
2075b05db6
@ -1,3 +1,17 @@
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2004-11-20 Richard Earnshaw <rearnsha@arm.com>
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* arm.c (arm_override_options): Use arm_ld_sched rather than testing
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a bit in tune_flags.
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(const_double_needs_minipool): Likewise. Split most of the code out
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into ...
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(arm_const_double_inline_cost): ... new function here.
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* arm-protos.h (arm_const_double_inline_cost): Add prototype.
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* arm.h (EXTRA_CONSTRAINT_STR_ARM): Add D[abc] constraints for double-
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word constants of length 2, 3 and 4 insns respectively.
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(CONSTRAINT_LEN): The 'D' prefix is a 2-letter constraint.
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* arm.md (arm_movdi, movdf_soft_insn): Add alternatives for D[abc]
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constraints. Set insn lenghts accordingly.
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2004-11-19 Kazu Hirata <kazu@cs.umass.edu>
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* basic-block.h (edge_def): Add dest_idx.
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@ -89,6 +89,7 @@ extern rtx arm_gen_compare_reg (RTX_CODE, rtx, rtx);
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extern rtx arm_gen_return_addr_mask (void);
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extern void arm_reload_in_hi (rtx *);
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extern void arm_reload_out_hi (rtx *);
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extern int arm_const_double_inline_cost (rtx);
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extern const char *fp_immediate_constant (rtx);
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extern const char *output_call (rtx *);
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extern const char *output_call_mem (rtx *);
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@ -1163,7 +1163,7 @@ arm_override_options (void)
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/* For processors with load scheduling, it never costs more than
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2 cycles to load a constant, and the load scheduler may well
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reduce that to 1. */
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if (tune_flags & FL_LDSCHED)
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if (arm_ld_sched)
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arm_constant_limit = 1;
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/* On XScale the longer latency of a load makes it more difficult
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@ -7258,43 +7258,52 @@ push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
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minipool_fix_tail = fix;
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}
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/* Determine if a CONST_DOUBLE should be pushed to the minipool */
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static bool
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const_double_needs_minipool (rtx val)
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/* Return the cost of synthesising the const_double VAL inline.
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Returns the number of insns needed, or 99 if we don't know how to
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do it. */
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int
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arm_const_double_inline_cost (rtx val)
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{
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long parts[2];
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/* thumb only knows to load a CONST_DOUBLE from memory at the moment */
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if (TARGET_THUMB)
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return true;
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if (GET_MODE (val) == DFmode)
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{
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REAL_VALUE_TYPE r;
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if (!TARGET_SOFT_FLOAT)
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return true;
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return 99;
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REAL_VALUE_FROM_CONST_DOUBLE (r, val);
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REAL_VALUE_TO_TARGET_DOUBLE (r, parts);
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}
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else if (GET_MODE (val) != VOIDmode)
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return true;
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return 99;
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else
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{
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parts[0] = CONST_DOUBLE_LOW (val);
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parts[1] = CONST_DOUBLE_HIGH (val);
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}
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return (arm_gen_constant (SET, SImode, NULL_RTX, parts[0],
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NULL_RTX, NULL_RTX, 0, 0)
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+ arm_gen_constant (SET, SImode, NULL_RTX, parts[1],
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NULL_RTX, NULL_RTX, 0, 0));
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}
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/* Determine if a CONST_DOUBLE should be pushed to the minipool */
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static bool
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const_double_needs_minipool (rtx val)
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{
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/* thumb only knows to load a CONST_DOUBLE from memory at the moment */
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if (TARGET_THUMB)
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return true;
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/* Don't push anything to the minipool if a CONST_DOUBLE can be built with
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a few ALU insns directly. On balance, the optimum is likely to be around
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3 insns, except when there are no load delay slots where it should be 4.
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When optimizing for size, a limit of 3 allows saving at least one word
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except for cases where a single minipool entry could be shared more than
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2 times which is rather unlikely to outweight the overall savings. */
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return ( arm_gen_constant (SET, SImode, NULL_RTX, parts[0],
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NULL_RTX, NULL_RTX, 0, 0)
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+ arm_gen_constant (SET, SImode, NULL_RTX, parts[1],
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NULL_RTX, NULL_RTX, 0, 0)
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> ((optimize_size || (tune_flags & FL_LDSCHED)) ? 3 : 4));
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return (arm_const_double_inline_cost (val)
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> ((optimize_size || arm_ld_sched) ? 3 : 4));
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}
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/* Scan INSN and note any of its operands that need fixing.
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@ -1309,27 +1309,39 @@ enum reg_class
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`S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
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address. This means that the symbol is in the text segment and can be
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accessed without using a load.
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'D' Prefixes a number of const_double operands where:
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'Da' is a constant that takes two ARM insns to load.
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'Db' takes three ARM insns.
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'Dc' takes four ARM insns, if we allow that in this compilation.
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'U' Prefixes an extended memory constraint where:
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'Uv' is an address valid for VFP load/store insns.
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'Uy' is an address valid for iwmmxt load/store insns.
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'Uq' is an address valid for ldrsb. */
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#define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
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(((C) == 'Q') ? (GET_CODE (OP) == MEM \
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&& GET_CODE (XEXP (OP, 0)) == REG) : \
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((C) == 'R') ? (GET_CODE (OP) == MEM \
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&& GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
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&& CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
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((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
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((C) == 'T') ? cirrus_memory_offset (OP) : \
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#define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
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(((C) == 'D') ? (GET_CODE (OP) == CONST_DOUBLE \
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&& (((STR)[1] == 'a' \
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&& arm_const_double_inline_cost (OP) == 2) \
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|| ((STR)[1] == 'b' \
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&& arm_const_double_inline_cost (OP) == 3) \
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|| ((STR)[1] == 'c' \
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&& arm_const_double_inline_cost (OP) == 4 \
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&& !(optimize_size || arm_ld_sched)))) : \
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((C) == 'Q') ? (GET_CODE (OP) == MEM \
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&& GET_CODE (XEXP (OP, 0)) == REG) : \
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((C) == 'R') ? (GET_CODE (OP) == MEM \
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&& GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
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&& CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
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((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
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((C) == 'T') ? cirrus_memory_offset (OP) : \
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((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
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((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
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((C) == 'U' && (STR)[1] == 'q') \
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? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
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: 0)
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((C) == 'U' && (STR)[1] == 'q') \
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? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
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: 0)
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#define CONSTRAINT_LEN(C,STR) \
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((C) == 'U' ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
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(((C) == 'U' || (C) == 'D') ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
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#define EXTRA_CONSTRAINT_THUMB(X, C) \
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((C) == 'Q' ? (GET_CODE (X) == MEM \
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@ -4156,18 +4156,18 @@
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)
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(define_insn "*arm_movdi"
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[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r ,m")
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(match_operand:DI 1 "di_operand" "rIK,mi,r"))]
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[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m")
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(match_operand:DI 1 "di_operand" "rIKDa,Db,Dc,mi,r"))]
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"TARGET_ARM
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&& !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP))
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&& !TARGET_IWMMXT"
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"*
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return (output_move_double (operands));
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"
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[(set_attr "length" "8")
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(set_attr "type" "*,load2,store2")
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(set_attr "pool_range" "*,1020,*")
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(set_attr "neg_pool_range" "*,1008,*")]
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[(set_attr "length" "8,12,16,8,8")
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(set_attr "type" "*,*,*,load2,store2")
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(set_attr "pool_range" "*,*,*,1020,*")
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(set_attr "neg_pool_range" "*,*,*,1008,*")]
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)
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;; We can't actually do base+index doubleword loads if the index and
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@ -5165,13 +5165,13 @@
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)
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(define_insn "*movdf_soft_insn"
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[(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,m")
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(match_operand:DF 1 "soft_df_operand" "r,mF,r"))]
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[(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,r,r,m")
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(match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,r"))]
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"TARGET_ARM && TARGET_SOFT_FLOAT
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"
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"* return output_move_double (operands);"
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[(set_attr "length" "8,8,8")
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(set_attr "type" "*,load2,store2")
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[(set_attr "length" "8,12,16,8,8")
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(set_attr "type" "*,*,*,load2,store2")
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(set_attr "pool_range" "1020")
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(set_attr "neg_pool_range" "1008")]
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)
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