(shiftcosts, genshifty_op): Add SH3 support.
From-SVN: r9813
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6b005b889e
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20b04867c8
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@ -36,6 +36,7 @@
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#define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
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#define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
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#define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
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#define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
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/* ??? The pragma interrupt support will not work for SH3. */
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/* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
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/* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
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output code for the next function appropriate for an interrupt handler. */
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output code for the next function appropriate for an interrupt handler. */
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int pragma_interrupt;
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int pragma_interrupt;
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@ -735,6 +736,9 @@ shiftcosts (x)
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/* If shift by a non constant, then this will be expensive. */
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/* If shift by a non constant, then this will be expensive. */
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if (GET_CODE (XEXP (x, 1)) != CONST_INT)
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if (GET_CODE (XEXP (x, 1)) != CONST_INT)
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{
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{
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if (TARGET_SH3)
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return 2;
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/* If not an sh3 then we don't even have an instruction for it. */
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return 20;
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return 20;
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}
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}
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@ -836,6 +840,8 @@ gen_ashift (type, n, reg)
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/* Output RTL to split a constant shift into its component SH constant
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/* Output RTL to split a constant shift into its component SH constant
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shift instructions. */
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shift instructions. */
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/* ??? For SH3, should reject constant shifts when slower than loading the
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shift count into a register? */
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int
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int
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gen_shifty_op (code, operands)
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gen_shifty_op (code, operands)
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@ -884,6 +890,13 @@ expand_ashiftrt (operands)
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tree func_name;
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tree func_name;
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int value;
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int value;
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if (TARGET_SH3 && GET_CODE (operands[2]) != CONST_INT)
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{
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rtx count = copy_to_mode_reg (SImode, operands[2]);
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emit_insn (gen_negsi2 (count, count));
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emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
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return 1;
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}
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if (GET_CODE (operands[2]) != CONST_INT)
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if (GET_CODE (operands[2]) != CONST_INT)
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return 0;
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return 0;
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