[RS6000] PR89271, gcc.target/powerpc/vsx-simode2.c
This patch makes a number of corrections to rs6000_register_move_cost, adds a new register union class, GEN_OR_VSX_REGS, and adjusts insn alternative costs to suit. The patch initially just corrected register move cost when direct moves are available, but that resulted in regressions. Inspection of those regressions showed ALL_REGS being used as the register allocno class, which isn't ideal. gcc/doc/tm.texi says: "You should define a class for the union of two classes whenever some instruction allows both classes". Thus, define GEN_OR_VSX_REGS for the register allocator. (IRA wants to use the union of two register classes when the costs of the classes are below memory cost, which happens more often with the low direct move cost.) As per https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89271#c11 we ought to be returning the minimal cost for union classes. That can be done by rs6000_register_move_cost testing for vsx first, where the number of regs for a given mode might be smaller than the same mode in gprs, and changing the LINK_OR_CTR_REGS case to exclude SPEC_OR_GEN_REGS and NON_FLOAT_REGS. I removed the VECTOR_MEM_VSX_P test since that leads to silly results for scalar mode moves between altivec and float when TARGET_VSX. eg. rs6000_register_move_cost:, ret=2, mode=DF, from=FLOAT_REGS, to=FLOAT_REGS rs6000_register_move_cost:, ret=16, mode=DF, from=FLOAT_REGS, to=ALTIVEC_REGS rs6000_register_move_cost:, ret=2, mode=DF, from=FLOAT_REGS, to=VSX_REGS The patch also fixes wrong results for moves within and between any of the non-gpr, non-vsx special reg classes. The comment about "moving between two similar registers is just one instruction" is false. We can't move lr to ctr directly, for example. I believe the intent of the "reg_classes_intersect_p (to, from)" was to cover moves within float or altivec, so I moved that test inside the code handling vsx, and made sure the intersection wasn't anything besides vsx by masking off everything else. Masking isn't strictly necessary at the moment, but would be if we create a GEN_OR_ALTIVEC_REGS class some time in the future. TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS is needed for rs6000 in order to fix the 20% cactus_adm spec regression when using GEN_OR_VSX_REGS as an allocno class. It is similar to the aarch64 version but without any selection by regno mode if the best class is a union class. PR target/89271 * config/rs6000/rs6000.h (enum reg_class, REG_CLASS_NAMES), (REG_CLASS_CONTENTS): Add GEN_OR_VSX_REGS class. * config/rs6000/rs6000.c (rs6000_register_move_cost): Correct cost for general <-> vsx when direct moves are available. Cost union classes at minimal cost for any reg in the class. Correct calculation for moves between vsx, float, and altivec. Don't return a low cost for moves between special regs. Don't use hard coded register numbers. (TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): Define. (rs6000_ira_change_pseudo_allocno_class): New function. * config/rs6000/rs6000.md (movsi_internal1, mov<mode>_internal), (movdi_internal32, movdi_internal64): Remove '*' from vsx register alternatives. (movsi_internal1): Don't disparage vector alternatives. (mov<mode>_internal): Likewise, excepting alternative that will be split. * config/rs6000/vsx.md (vsx_splat_<mode>_reg): Don't disparage we <- b alternative. From-SVN: r271022
This commit is contained in:
Alan Modra
Alan Modra
parent
3407d1658f
commit
20d70cd271
@ -1,3 +1,25 @@
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2019-05-09 Alan Modra <amodra@gmail.com>
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PR target/89271
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* config/rs6000/rs6000.h (enum reg_class, REG_CLASS_NAMES),
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(REG_CLASS_CONTENTS): Add GEN_OR_VSX_REGS class.
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* config/rs6000/rs6000.c (rs6000_register_move_cost): Correct
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cost for general <-> vsx when direct moves are available.
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Cost union classes at minimal cost for any reg in the class.
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Correct calculation for moves between vsx, float, and altivec.
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Don't return a low cost for moves between special regs. Don't
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use hard coded register numbers.
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(TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): Define.
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(rs6000_ira_change_pseudo_allocno_class): New function.
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* config/rs6000/rs6000.md (movsi_internal1, mov<mode>_internal),
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(movdi_internal32, movdi_internal64): Remove '*' from vsx register
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alternatives.
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(movsi_internal1): Don't disparage vector alternatives.
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(mov<mode>_internal): Likewise, excepting alternative that
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will be split.
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* config/rs6000/vsx.md (vsx_splat_<mode>_reg): Don't disparage
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we <- b alternative.
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2019-05-08 Jakub Jelinek <jakub@redhat.com>
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PR c++/59813
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@ -1729,6 +1729,9 @@ static const struct attribute_spec rs6000_attribute_table[] =
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#define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
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#undef TARGET_MEMORY_MOVE_COST
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#define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
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#undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
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#define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
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rs6000_ira_change_pseudo_allocno_class
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#undef TARGET_CANNOT_COPY_INSN_P
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#define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
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#undef TARGET_RTX_COSTS
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@ -34648,22 +34651,54 @@ rs6000_register_move_cost (machine_mode mode,
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reg_class_t from, reg_class_t to)
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{
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int ret;
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reg_class_t rclass;
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if (TARGET_DEBUG_COST)
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dbg_cost_ctrl++;
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/* Moves from/to GENERAL_REGS. */
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if (reg_classes_intersect_p (to, GENERAL_REGS)
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|| reg_classes_intersect_p (from, GENERAL_REGS))
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/* If we have VSX, we can easily move between FPR or Altivec registers,
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otherwise we can only easily move within classes.
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Do this first so we give best-case answers for union classes
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containing both gprs and vsx regs. */
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HARD_REG_SET to_vsx, from_vsx;
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COPY_HARD_REG_SET (to_vsx, reg_class_contents[to]);
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AND_HARD_REG_SET (to_vsx, reg_class_contents[VSX_REGS]);
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COPY_HARD_REG_SET (from_vsx, reg_class_contents[from]);
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AND_HARD_REG_SET (from_vsx, reg_class_contents[VSX_REGS]);
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if (!hard_reg_set_empty_p (to_vsx)
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&& !hard_reg_set_empty_p (from_vsx)
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&& (TARGET_VSX
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|| hard_reg_set_intersect_p (to_vsx, from_vsx)))
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{
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reg_class_t rclass = from;
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if (! reg_classes_intersect_p (to, GENERAL_REGS))
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rclass = to;
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int reg = FIRST_FPR_REGNO;
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if (TARGET_VSX
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|| (TEST_HARD_REG_BIT (to_vsx, FIRST_ALTIVEC_REGNO)
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&& TEST_HARD_REG_BIT (from_vsx, FIRST_ALTIVEC_REGNO)))
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reg = FIRST_ALTIVEC_REGNO;
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ret = 2 * hard_regno_nregs (reg, mode);
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}
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/* Moves from/to GENERAL_REGS. */
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else if ((rclass = from, reg_classes_intersect_p (to, GENERAL_REGS))
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|| (rclass = to, reg_classes_intersect_p (from, GENERAL_REGS)))
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{
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if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
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{
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if (TARGET_DIRECT_MOVE)
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{
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if (rs6000_tune == PROCESSOR_POWER9)
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ret = 2 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
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else
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ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
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/* SFmode requires a conversion when moving between gprs
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and vsx. */
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if (mode == SFmode)
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ret += 2;
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}
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else
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ret = (rs6000_memory_move_cost (mode, rclass, false)
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+ rs6000_memory_move_cost (mode, GENERAL_REGS, false));
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}
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/* It's more expensive to move CR_REGS than CR0_REGS because of the
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shift. */
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@ -34676,24 +34711,14 @@ rs6000_register_move_cost (machine_mode mode,
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|| rs6000_tune == PROCESSOR_POWER7
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|| rs6000_tune == PROCESSOR_POWER8
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|| rs6000_tune == PROCESSOR_POWER9)
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&& reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
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ret = 6 * hard_regno_nregs (0, mode);
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&& reg_class_subset_p (rclass, SPECIAL_REGS))
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ret = 6 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
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else
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/* A move will cost one instruction per GPR moved. */
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ret = 2 * hard_regno_nregs (0, mode);
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ret = 2 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
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}
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/* If we have VSX, we can easily move between FPR or Altivec registers. */
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else if (VECTOR_MEM_VSX_P (mode)
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&& reg_classes_intersect_p (to, VSX_REGS)
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&& reg_classes_intersect_p (from, VSX_REGS))
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ret = 2 * hard_regno_nregs (FIRST_FPR_REGNO, mode);
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/* Moving between two similar registers is just one instruction. */
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else if (reg_classes_intersect_p (to, from))
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ret = (FLOAT128_2REG_P (mode)) ? 4 : 2;
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/* Everything else has to go through GENERAL_REGS. */
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else
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ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
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@ -34746,6 +34771,64 @@ rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
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return ret;
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}
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/* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
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The register allocator chooses GEN_OR_VSX_REGS for the allocno
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class if GENERAL_REGS and VSX_REGS cost is lower than the memory
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cost. This happens a lot when TARGET_DIRECT_MOVE makes the register
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move cost between GENERAL_REGS and VSX_REGS low.
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It might seem reasonable to use a union class. After all, if usage
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of vsr is low and gpr high, it might make sense to spill gpr to vsr
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rather than memory. However, in cases where register pressure of
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both is high, like the cactus_adm spec test, allowing
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GEN_OR_VSX_REGS as the allocno class results in bad decisions in
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the first scheduling pass. This is partly due to an allocno of
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GEN_OR_VSX_REGS wrongly contributing to the GENERAL_REGS pressure
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class, which gives too high a pressure for GENERAL_REGS and too low
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for VSX_REGS. So, force a choice of the subclass here.
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The best class is also the union if GENERAL_REGS and VSX_REGS have
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the same cost. In that case we do use GEN_OR_VSX_REGS as the
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allocno class, since trying to narrow down the class by regno mode
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is prone to error. For example, SImode is allowed in VSX regs and
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in some cases (eg. gcc.target/powerpc/p9-xxbr-3.c do_bswap32_vect)
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it would be wrong to choose an allocno of GENERAL_REGS based on
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SImode. */
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static reg_class_t
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rs6000_ira_change_pseudo_allocno_class (int regno ATTRIBUTE_UNUSED,
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reg_class_t allocno_class,
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reg_class_t best_class)
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{
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switch (allocno_class)
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{
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case GEN_OR_VSX_REGS:
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/* best_class must be a subset of allocno_class. */
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gcc_checking_assert (best_class == GEN_OR_VSX_REGS
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|| best_class == GEN_OR_FLOAT_REGS
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|| best_class == VSX_REGS
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|| best_class == ALTIVEC_REGS
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|| best_class == FLOAT_REGS
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|| best_class == GENERAL_REGS
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|| best_class == BASE_REGS);
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/* Use best_class but choose wider classes when copying from the
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wider class to best_class is cheap. This mimics IRA choice
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of allocno class. */
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if (best_class == BASE_REGS)
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return GENERAL_REGS;
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if (TARGET_VSX
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&& (best_class == FLOAT_REGS || best_class == ALTIVEC_REGS))
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return VSX_REGS;
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return best_class;
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default:
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break;
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}
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return allocno_class;
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}
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/* Returns a code for a target-specific builtin that implements
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reciprocal of the function, or NULL_TREE if not available. */
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@ -1141,6 +1141,7 @@ enum reg_class
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VRSAVE_REGS,
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VSCR_REGS,
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GEN_OR_FLOAT_REGS,
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GEN_OR_VSX_REGS,
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LINK_REGS,
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CTR_REGS,
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LINK_OR_CTR_REGS,
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@ -1169,6 +1170,7 @@ enum reg_class
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"VRSAVE_REGS", \
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"VSCR_REGS", \
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"GEN_OR_FLOAT_REGS", \
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"GEN_OR_VSX_REGS", \
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"LINK_REGS", \
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"CTR_REGS", \
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"LINK_OR_CTR_REGS", \
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@ -1205,6 +1207,8 @@ enum reg_class
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{ 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \
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/* GEN_OR_FLOAT_REGS. */ \
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{ 0xffffffff, 0xffffffff, 0x00000000, 0x00004008 }, \
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/* GEN_OR_VSX_REGS. */ \
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{ 0xffffffff, 0xffffffff, 0xffffffff, 0x00004008 }, \
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/* LINK_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, \
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/* CTR_REGS. */ \
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@ -6830,10 +6830,10 @@
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;; MF%1 MT%0 NOP
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(define_insn "*movsi_internal1"
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[(set (match_operand:SI 0 "nonimmediate_operand"
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"=r, r, r, ?*wI, ?*wH,
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m, ?Z, ?Z, r, r,
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r, ?*wIwH, ?*wJwK, ?*wJwK, ?*wu,
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?*wJwK, ?*wH, ?*wK, ?*wIwH, ?r,
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"=r, r, r, wI, wH,
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m, Z, Z, r, r,
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r, wIwH, wJwK, wJwK, wu,
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wJwK, wH, wK, wIwH, r,
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r, *h, *h")
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(match_operand:SI 1 "input_operand"
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@ -7104,13 +7104,13 @@
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;; MTVSRWZ MF%1 MT%1 NOP
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(define_insn "*mov<mode>_internal"
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[(set (match_operand:QHI 0 "nonimmediate_operand"
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"=r, r, ?*wJwK, m, Z, r,
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?*wJwK, ?*wJwK, ?*wJwK, ?*wK, ?*wK, r,
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?*wJwK, r, *c*l, *h")
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"=r, r, wJwK, m, Z, r,
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wJwK, wJwK, wJwK, wK, ?wK, r,
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wJwK, r, *c*l, *h")
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(match_operand:QHI 1 "input_operand"
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"r, m, Z, r, wJwK, i,
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wJwK, O, wM, wB, wS, ?*wJwK,
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wJwK, O, wM, wB, wS, wJwK,
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r, *h, r, 0"))]
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"gpc_reg_operand (operands[0], <MODE>mode)
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@ -8671,8 +8671,8 @@
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[(set (match_operand:DI 0 "nonimmediate_operand"
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"=Y, r, r, m, ^d, ^d,
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r, wY, Z, ^wb, $wv, ^wi,
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*wo, *wo, *wv, *wi, *wi, *wv,
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*wv")
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wo, wo, wv, wi, *i, wv,
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wv")
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(match_operand:DI 1 "input_operand"
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"r, Y, r, ^d, m, ^d,
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@ -8751,9 +8751,9 @@
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[(set (match_operand:DI 0 "nonimmediate_operand"
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"=YZ, r, r, r, r, r,
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m, ^d, ^d, wY, Z, $wb,
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$wv, ^wi, *wo, *wo, *wv, *wi,
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*wi, *wv, *wv, r, *h, *h,
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?*r, ?*wg, ?*r, ?*wj")
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$wv, ^wi, wo, wo, wv, wi,
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wi, wv, wv, r, *h, *h,
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?r, ?wg, ?r, ?wj")
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(match_operand:DI 1 "input_operand"
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"r, YZ, r, I, L, nF,
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@ -4106,7 +4106,7 @@
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})
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(define_insn "vsx_splat_<mode>_reg"
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[(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSX_D:VSa>,?we")
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[(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSX_D:VSa>,we")
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(vec_duplicate:VSX_D
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(match_operand:<VS_scalar> 1 "gpc_reg_operand" "<VSX_D:VS_64reg>,b")))]
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"VECTOR_MEM_VSX_P (<MODE>mode)"
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