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Patch from Gary McGary to fix i960 problem with out-of-range shifts. 

* i960.h (hard_regno_mode_ok): Changed to function from array of
 	unsigned.
	(HARD_REGNO_MODE_OK): Call function instead of testing bit.
	* i960.c (hard_regno_mode_ok): Changed to function from array of
 	unsigned.

From-SVN: r19745
This commit is contained in:
Jim Wilson 1998-05-14 13:00:18 +00:00 committed by Jim Wilson
parent f2ee215beb
commit 2129b0816f
3 changed files with 54 additions and 30 deletions
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8
gcc/ChangeLog
View File

@ -1,3 +1,11 @@
Thu May 14 12:58:21 1998 Jim Wilson <wilson@cygnus.com>
* i960.h (hard_regno_mode_ok): Changed to function from array of
unsigned.
(HARD_REGNO_MODE_OK): Call function instead of testing bit.
* i960.c (hard_regno_mode_ok): Changed to function from array of
unsigned.
Thu May 14 08:41:46 1998 J"orn Rennecke <amylaar@cygnus.co.uk>
* reload.c (remove_replacements): New function.

71
gcc/config/i960/i960.c
View File

@ -2067,40 +2067,57 @@ i960_alignment (size, align)
}
#endif
/* Modes for condition codes. */
#define C_MODES \
((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
/* Modes for single-word (and smaller) quantities. */
#define S_MODES \
(~C_MODES \
& ~ ((1 << (int) DImode) | (1 << (int) TImode) \
| (1 << (int) DFmode) | (1 << (int) XFmode)))
int
hard_regno_mode_ok (regno, mode)
int regno;
enum machine_mode mode;
{
if (regno < 32)
{
switch (mode)
{
case CCmode: case CC_UNSmode: case CC_CHKmode:
return 0;
/* Modes for double-word (and smaller) quantities. */
#define D_MODES \
(~C_MODES \
& ~ ((1 << (int) TImode) | (1 << (int) XFmode)))
case DImode: case DFmode:
return (regno & 1) == 0;
/* Modes for quad-word quantities. */
#define T_MODES (~C_MODES)
case TImode: case XFmode:
return (regno & 3) == 0;
/* Modes for single-float quantities. */
#define SF_MODES ((1 << (int) SFmode))
default:
return 1;
}
}
else if (regno >= 32 && regno < 36)
{
switch (mode)
{
case SFmode: case DFmode: case XFmode:
case SCmode: case DCmode:
return 1;
/* Modes for double-float quantities. */
#define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
default:
return 0;
}
}
else if (regno == 36)
{
switch (mode)
{
case CCmode: case CC_UNSmode: case CC_CHKmode:
return 1;
/* Modes for quad-float quantities. */
#define XF_MODES (DF_MODES | (1 << (int) XFmode) | (1 << (int) DCmode))
default:
return 0;
}
}
else if (regno == 37)
return 0;
unsigned int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] = {
T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
XF_MODES, XF_MODES, XF_MODES, XF_MODES, C_MODES};
abort ();
}
/* Return the minimum alignment of an expression rtx X in bytes. This takes

5
gcc/config/i960/i960.h
View File

@ -506,9 +506,8 @@ extern int target_flags;
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
On 80960, the cpu registers can hold any mode but the float registers
can only hold SFmode, DFmode, or XFmode. */
extern unsigned int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
((hard_regno_mode_ok[REGNO] & (1 << (int) (MODE))) != 0)
extern int hard_regno_mode_ok ();
#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok ((REGNO), (MODE))
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.