ev5.md: Don't combine shift and mvi insns in one reservation.
* config/alpha/ev5.md: Don't combine shift and mvi insns in one reservation. From-SVN: r54453
This commit is contained in:
parent
158d04aa28
commit
21442990fd
|
@ -64,9 +64,14 @@
|
|||
(eq_attr "type" "jsr"))
|
||||
"ev5_e1")
|
||||
|
||||
(define_insn_reservation "ev5_shiftmvi" 2
|
||||
(define_insn_reservation "ev5_shift" 1
|
||||
(and (eq_attr "cpu" "ev5")
|
||||
(eq_attr "type" "shift,mvi"))
|
||||
(eq_attr "type" "shift"))
|
||||
"ev5_e0")
|
||||
|
||||
(define_insn_reservation "ev5_mvi" 2
|
||||
(and (eq_attr "cpu" "ev5")
|
||||
(eq_attr "type" "mvi"))
|
||||
"ev5_e0")
|
||||
|
||||
(define_insn_reservation "ev5_cmov" 2
|
||||
|
@ -119,7 +124,7 @@
|
|||
; Model this instead with increased latency on the input instruction.
|
||||
|
||||
(define_bypass 3
|
||||
"ev5_ld,ev5_shiftmvi,ev5_cmov,ev5_iadd,ev5_ilogcmp"
|
||||
"ev5_ld,ev5_shift,ev5_mvi,ev5_cmov,ev5_iadd,ev5_ilogcmp"
|
||||
"ev5_imull,ev5_imulq,ev5_imulh")
|
||||
|
||||
(define_bypass 9 "ev5_imull" "ev5_imull,ev5_imulq,ev5_imulh")
|
||||
|
|
Loading…
Reference in New Issue