avx512fintrin.h (_mm512_kmov): New.
gcc/ * config/i386/avx512fintrin.h (_mm512_kmov): New. * config/i386/i386.c (IX86_BUILTIN_KMOV16): Ditto. (__builtin_ia32_kmov16): Ditto. * config/i386/i386.md (UNSPEC_KMOV): New. (kmovw): Ditto. testsuite/gcc/ * gcc.target/i386/avx512f-kmovw-1.c: New. Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com> From-SVN: r206958
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@ -28,6 +28,15 @@
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going until we reach the size of the line.
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* Makefile.in: Add vec.o to OBJS-libcommon
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2014-01-23 Kirill Yukhin <kirill.yukhin@intel.com>
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Ilya Tocar <ilya.tocar@intel.com>
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* config/i386/avx512fintrin.h (_mm512_kmov): New.
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* config/i386/i386.c (IX86_BUILTIN_KMOV16): Ditto.
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(__builtin_ia32_kmov16): Ditto.
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* config/i386/i386.md (UNSPEC_KMOV): New.
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(kmovw): Ditto.
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2014-01-23 Kirill Yukhin <kirill.yukhin@intel.com>
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* config/i386/avx512fintrin.h (_mm512_loadu_si512): Rename.
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@ -12688,6 +12688,13 @@ _mm_mask_cmp_ss_mask (__mmask8 __M, __m128 __X, __m128 __Y, const int __P)
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M,_MM_FROUND_CUR_DIRECTION))
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#endif
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extern __inline __mmask16
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_kmov (__mmask16 __A)
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{
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return __builtin_ia32_kmov16 (__A);
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}
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#ifdef __DISABLE_AVX512F__
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#undef __DISABLE_AVX512F__
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#pragma GCC pop_options
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@ -28376,6 +28376,7 @@ enum ix86_builtins
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IX86_BUILTIN_KUNPCKBW,
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IX86_BUILTIN_KXNOR16,
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IX86_BUILTIN_KXOR16,
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IX86_BUILTIN_KMOV16,
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/* Alternate 4 and 8 element gather/scatter for the vectorizer
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where all operands are 32-byte or 64-byte wide respectively. */
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@ -30083,6 +30084,7 @@ static const struct builtin_description bdesc_args[] =
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{ OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
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{ OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
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{ OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
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{ OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
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/* SHA */
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{ OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
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@ -178,6 +178,9 @@
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;; For BMI2 support
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UNSPEC_PDEP
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UNSPEC_PEXT
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;; For AVX512F support
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UNSPEC_KMOV
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])
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(define_c_enum "unspecv" [
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@ -2288,6 +2291,20 @@
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]
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(const_string "SI")))])
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(define_insn "kmovw"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=k,k")
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(unspec:HI
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[(match_operand:HI 1 "nonimmediate_operand" "rm,k")]
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UNSPEC_KMOV))]
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"!(MEM_P (operands[0]) && MEM_P (operands[1])) && TARGET_AVX512F"
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"@
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kmovw\t{%k1, %0|%0, %k1}
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kmovw\t{%1, %0|%0, %1}";
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[(set_attr "mode" "HI")
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(set_attr "type" "mskmov")
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(set_attr "prefix" "vex")])
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(define_insn "*movhi_internal"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r ,r ,m ,Yk,Yk,rm")
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(match_operand:HI 1 "general_operand" "r ,rn,rm,rn,rm,Yk,Yk"))]
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@ -4,8 +4,13 @@
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* c-c++-common/cpp/warning-zero-in-literals-1.c: New test file.
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2014-01-23 Kirill Yukhin <kirill.yukhin@intel.com>
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Ilya Tocar <ilya.tocar@intel.com>
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* gcc.target/i386/avx512f-vmovdqu32-1.c: Fix intrinsic name.
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* gcc.target/i386/avx512f-kmovw-1.c: New.
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2014-01-23 Kirill Yukhin <kirill.yukhin@intel.com>
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* gcc.target/i386/avx512f-vmovdqu32-1.c: Fix intrinsic name.
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* gcc.target/i386/avx512f-vmovdqu32-2.c: Ditto.
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* gcc.target/i386/avx512f-vpcmpd-2.c: Ditto.
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* gcc.target/i386/avx512f-vpcmpq-2.c: Ditto.
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12
gcc/testsuite/gcc.target/i386/avx512f-kmovw-1.c
Normal file
12
gcc/testsuite/gcc.target/i386/avx512f-kmovw-1.c
Normal file
@ -0,0 +1,12 @@
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/* { dg-do compile } */
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/* { dg-options "-mavx512f -O2" } */
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/* { dg-final { scan-assembler "kmovw\[ \\t\]+\[^\n\]*%k\[1-7\]" } } */
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#include <immintrin.h>
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volatile __mmask16 k1;
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void
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avx512f_test ()
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{
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k1 = _mm512_kmov (11);
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}
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