mips.h (ISA_HAS_LOAD_DELAY, [...]): New macros.
* config/mips/mips.h (ISA_HAS_LOAD_DELAY, ISA_HAS_XFER_DELAY, ISA_HAS_FCMP_DELAY, ISA_HAS_HILO_INTERLOCKS): New macros. (PREDICATE_CODES): Add hilo_operand. * config/mips/mips.c (hilo_operand): New predicate. (mips_adjust_insn_length): Account for the number nops that might be needed to avoid hardware hazards. * config/mips/mips.md (dslot): Remove attribute. (hazard): New attribute. (can_delay): Use it. Check for calls, branches & jumps. (muldi3): Use the standard dmult pattern for mips16 code. (muldi3_internal, muldi3_internal2): Adjust conditions accordingly. From-SVN: r66952
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
f29d1b660c
commit
21c9500d3e
@ -1,3 +1,17 @@
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2003-05-19 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.h (ISA_HAS_LOAD_DELAY, ISA_HAS_XFER_DELAY,
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ISA_HAS_FCMP_DELAY, ISA_HAS_HILO_INTERLOCKS): New macros.
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(PREDICATE_CODES): Add hilo_operand.
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* config/mips/mips.c (hilo_operand): New predicate.
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(mips_adjust_insn_length): Account for the number nops that might
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be needed to avoid hardware hazards.
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* config/mips/mips.md (dslot): Remove attribute.
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(hazard): New attribute.
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(can_delay): Use it. Check for calls, branches & jumps.
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(muldi3): Use the standard dmult pattern for mips16 code.
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(muldi3_internal, muldi3_internal2): Adjust conditions accordingly.
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2003-05-19 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips-protos.h (final_prescan_insn,
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@ -1507,6 +1507,18 @@ const_float_1_operand (op, mode)
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return REAL_VALUES_EQUAL (d, dconst1);
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}
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/* Return true if OP is either the HI or LO register. */
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int
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hilo_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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return ((mode == VOIDmode || mode == GET_MODE (op))
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&& REG_P (op)
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&& (REGNO (op) == HI_REGNUM || REGNO (op) == LO_REGNUM));
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}
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/* Return nonzero if the code of this rtx pattern is EQ or NE. */
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int
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@ -9897,6 +9909,22 @@ mips_adjust_insn_length (insn, length)
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|| GET_CODE (insn) == CALL_INSN)))
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length += 4;
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/* See how many nops might be needed to avoid hardware hazards. */
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if (INSN_CODE (insn) >= 0)
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switch (get_attr_hazard (insn))
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{
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case HAZARD_NONE:
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break;
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case HAZARD_DELAY:
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length += 4;
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break;
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case HAZARD_HILO:
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length += 8;
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break;
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}
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/* All MIPS16 instructions are a measly two bytes. */
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if (TARGET_MIPS16)
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length /= 2;
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@ -945,6 +945,24 @@ extern void sbss_section PARAMS ((void));
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&& (ISA_MIPS32R2 \
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))
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/* True if the result of a load is not available to the next instruction.
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A nop will then be needed between instructions like "lw $4,..."
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and "addiu $4,$4,1". */
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#define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
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&& !TARGET_MIPS3900 \
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&& !TARGET_MIPS16)
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/* Likewise mtc1 and mfc1. */
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#define ISA_HAS_XFER_DELAY (mips_isa <= 3)
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/* Likewise floating-point comparisons. */
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#define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
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/* True if mflo and mfhi can be immediately followed by instructions
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which write to the HI and LO registers. Most targets require a
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two-instruction gap. */
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#define ISA_HAS_HILO_INTERLOCKS (TARGET_MIPS5500 || TARGET_SB1)
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/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
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-mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
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-mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
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@ -3374,7 +3392,8 @@ typedef struct mips_args {
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REG, MEM}}, \
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{"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
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CONST_DOUBLE, CONST }}, \
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{"fcc_register_operand", { REG, SUBREG }},
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{"fcc_register_operand", { REG, SUBREG }}, \
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{"hilo_operand", { REG }},
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/* A list of predicates that do special things with modes, and so
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should not elicit warnings for VOIDmode match_operand. */
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@ -193,17 +193,33 @@
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"default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r8000,sb1,sr71000"
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(const (symbol_ref "mips_cpu_attr")))
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;; Does the instruction have a mandatory delay slot?
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;; The 3900, is (mostly) mips1, but does not have a mandatory load delay
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;; slot.
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(define_attr "dslot" "no,yes"
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(if_then_else (ior (eq_attr "type" "branch,jump,call,xfer,hilo,fcmp")
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(and (eq_attr "type" "load")
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(and (eq (symbol_ref "mips_isa") (const_int 1))
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(and (eq (symbol_ref "mips16") (const_int 0))
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(eq_attr "cpu" "!r3900")))))
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(const_string "yes")
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(const_string "no")))
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;; The type of hardware hazard associated with this instruction.
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;; DELAY means that the next instruction cannot read the result
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;; of this one. HILO means that the next two instructions cannot
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;; write to HI or LO.
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(define_attr "hazard" "none,delay,hilo"
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(cond [(and (eq_attr "type" "load")
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(ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
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(const_string "delay")
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(and (eq_attr "type" "xfer")
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(ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
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(const_string "delay")
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(and (eq_attr "type" "fcmp")
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(ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
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(const_string "delay")
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;; The r4000 multiplication patterns include an mflo instruction.
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(and (eq_attr "type" "imul")
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(ne (symbol_ref "TARGET_MIPS4000") (const_int 0)))
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(const_string "hilo")
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(and (eq_attr "type" "hilo")
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(and (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0))
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(match_operand 1 "hilo_operand" "")))
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(const_string "hilo")]
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(const_string "none")))
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;; Is it a single instruction?
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(define_attr "single_insn" "no,yes"
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@ -211,8 +227,9 @@
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;; Can the instruction be put into a delay slot?
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(define_attr "can_delay" "no,yes"
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(if_then_else (and (eq_attr "dslot" "no")
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(eq_attr "single_insn" "yes"))
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(if_then_else (and (eq_attr "type" "!branch,call,jump")
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(and (eq_attr "hazard" "none")
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(eq_attr "single_insn" "yes")))
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(const_string "yes")
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(const_string "no")))
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@ -2274,7 +2291,7 @@
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"
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{
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if (GENERATE_MULT3_DI || TARGET_MIPS4000 || TARGET_MIPS16)
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if (GENERATE_MULT3_DI || TARGET_MIPS4000)
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emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2]));
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else
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emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
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@ -2287,7 +2304,7 @@
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(match_operand:DI 2 "register_operand" "d")))
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(clobber (match_scratch:DI 3 "=h"))
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(clobber (match_scratch:DI 4 "=a"))]
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"TARGET_64BIT && !TARGET_MIPS4000 && !TARGET_MIPS16"
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"TARGET_64BIT && !TARGET_MIPS4000"
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"dmult\\t%1,%2"
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[(set_attr "type" "imul")
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(set_attr "mode" "DI")])
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@ -2299,7 +2316,7 @@
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(clobber (match_scratch:DI 3 "=h"))
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(clobber (match_scratch:DI 4 "=l"))
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(clobber (match_scratch:DI 5 "=a"))]
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"TARGET_64BIT && (GENERATE_MULT3_DI || TARGET_MIPS4000 || TARGET_MIPS16)"
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"TARGET_64BIT && (GENERATE_MULT3_DI || TARGET_MIPS4000)"
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{
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if (GENERATE_MULT3_DI)
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return "dmult\t%0,%1,%2";
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