i386.h (processor_costs): Add new fields fadd, fmul, fdiv, fabs, fchs and fsqrt to costs structure.
* config/i386/i386.h (processor_costs): Add new fields fadd, fmul, fdiv, fabs, fchs and fsqrt to costs structure. (RTX_COSTS): Use these fields to determine the RTX costs of floating point addition/subtraction, multiplication, division, fabs, negation and square root respectively. * config/i386/i386.c (size_cost): Provide instruction sizes for these new fields. (i386_cost, i486_cost, pentium_cost, pentiumpro_cost, k6_cost, athlon_cost, pentium4_cost): Provide typical cycle counts for these new fields for all x86 processor variants. From-SVN: r57820
This commit is contained in:
Roger Sayle
Roger Sayle
parent
f42ee52fc0
commit
229b303adf
@ -1,3 +1,16 @@
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2002-10-04 Roger Sayle <roger@eyesopen.com>
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* config/i386/i386.h (processor_costs): Add new fields fadd,
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fmul, fdiv, fabs, fchs and fsqrt to costs structure.
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(RTX_COSTS): Use these fields to determine the RTX costs
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of floating point addition/subtraction, multiplication,
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division, fabs, negation and square root respectively.
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* config/i386/i386.c (size_cost): Provide instruction sizes
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for these new fields.
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(i386_cost, i486_cost, pentium_cost, pentiumpro_cost,
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k6_cost, athlon_cost, pentium4_cost): Provide typical cycle
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counts for these new fields for all x86 processor variants.
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2002-10-04 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
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* mips.c (mips_const_double_ok): Delete unused variable.
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@ -84,7 +84,14 @@ struct processor_costs size_cost = { /* costs for tunning for size */
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3, /* MMX or SSE register to integer */
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0, /* size of prefetch block */
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0, /* number of parallel prefetches */
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2, /* cost of FADD and FSUB insns. */
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2, /* cost of FMUL instruction. */
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2, /* cost of FDIV instruction. */
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2, /* cost of FABS instruction. */
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2, /* cost of FCHS instruction. */
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2, /* cost of FSQRT instruction. */
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};
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/* Processor costs (relative to an add) */
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static const
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struct processor_costs i386_cost = { /* 386 specific costs */
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@ -121,6 +128,12 @@ struct processor_costs i386_cost = { /* 386 specific costs */
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3, /* MMX or SSE register to integer */
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0, /* size of prefetch block */
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0, /* number of parallel prefetches */
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23, /* cost of FADD and FSUB insns. */
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27, /* cost of FMUL instruction. */
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88, /* cost of FDIV instruction. */
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22, /* cost of FABS instruction. */
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24, /* cost of FCHS instruction. */
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122, /* cost of FSQRT instruction. */
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};
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static const
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@ -158,6 +171,12 @@ struct processor_costs i486_cost = { /* 486 specific costs */
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3, /* MMX or SSE register to integer */
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0, /* size of prefetch block */
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0, /* number of parallel prefetches */
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8, /* cost of FADD and FSUB insns. */
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16, /* cost of FMUL instruction. */
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73, /* cost of FDIV instruction. */
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3, /* cost of FABS instruction. */
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3, /* cost of FCHS instruction. */
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83, /* cost of FSQRT instruction. */
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};
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static const
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@ -195,6 +214,12 @@ struct processor_costs pentium_cost = {
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3, /* MMX or SSE register to integer */
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0, /* size of prefetch block */
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0, /* number of parallel prefetches */
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3, /* cost of FADD and FSUB insns. */
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3, /* cost of FMUL instruction. */
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39, /* cost of FDIV instruction. */
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1, /* cost of FABS instruction. */
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1, /* cost of FCHS instruction. */
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70, /* cost of FSQRT instruction. */
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};
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static const
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@ -232,6 +257,12 @@ struct processor_costs pentiumpro_cost = {
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3, /* MMX or SSE register to integer */
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32, /* size of prefetch block */
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6, /* number of parallel prefetches */
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3, /* cost of FADD and FSUB insns. */
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5, /* cost of FMUL instruction. */
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56, /* cost of FDIV instruction. */
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2, /* cost of FABS instruction. */
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2, /* cost of FCHS instruction. */
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56, /* cost of FSQRT instruction. */
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};
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static const
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@ -269,6 +300,12 @@ struct processor_costs k6_cost = {
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6, /* MMX or SSE register to integer */
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32, /* size of prefetch block */
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1, /* number of parallel prefetches */
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2, /* cost of FADD and FSUB insns. */
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2, /* cost of FMUL instruction. */
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2, /* cost of FDIV instruction. */
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56, /* cost of FABS instruction. */
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2, /* cost of FCHS instruction. */
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56, /* cost of FSQRT instruction. */
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};
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static const
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@ -306,6 +343,12 @@ struct processor_costs athlon_cost = {
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5, /* MMX or SSE register to integer */
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64, /* size of prefetch block */
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6, /* number of parallel prefetches */
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4, /* cost of FADD and FSUB insns. */
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4, /* cost of FMUL instruction. */
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24, /* cost of FDIV instruction. */
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2, /* cost of FABS instruction. */
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2, /* cost of FCHS instruction. */
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35, /* cost of FSQRT instruction. */
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};
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static const
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@ -343,6 +386,12 @@ struct processor_costs pentium4_cost = {
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10, /* MMX or SSE register to integer */
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64, /* size of prefetch block */
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6, /* number of parallel prefetches */
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5, /* cost of FADD and FSUB insns. */
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7, /* cost of FMUL instruction. */
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43, /* cost of FDIV instruction. */
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2, /* cost of FABS instruction. */
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2, /* cost of FCHS instruction. */
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43, /* cost of FSQRT instruction. */
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};
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const struct processor_costs *ix86_cost = &pentium_cost;
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@ -75,6 +75,12 @@ struct processor_costs {
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const int prefetch_block; /* bytes moved to cache for prefetch. */
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const int simultaneous_prefetches; /* number of parallel prefetch
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operations. */
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const int fadd; /* cost of FADD and FSUB instructions. */
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const int fmul; /* cost of FMUL instruction. */
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const int fdiv; /* cost of FDIV instruction. */
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const int fabs; /* cost of FABS instruction. */
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const int fchs; /* cost of FCHS instruction. */
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const int fsqrt; /* cost of FSQRT instruction. */
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};
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extern const struct processor_costs *ix86_cost;
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@ -2632,7 +2638,9 @@ do { \
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break; \
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\
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case MULT: \
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if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
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if (FLOAT_MODE_P (GET_MODE (X))) \
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TOPLEVEL_COSTS_N_INSNS (ix86_cost->fmul); \
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else if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
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{ \
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unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
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int nbits = 0; \
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@ -2654,10 +2662,16 @@ do { \
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case UDIV: \
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case MOD: \
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case UMOD: \
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TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
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if (FLOAT_MODE_P (GET_MODE (X))) \
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TOPLEVEL_COSTS_N_INSNS (ix86_cost->fdiv); \
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else \
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TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
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break; \
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\
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case PLUS: \
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if (!TARGET_DECOMPOSE_LEA \
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if (FLOAT_MODE_P (GET_MODE (X))) \
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TOPLEVEL_COSTS_N_INSNS (ix86_cost->fadd); \
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else if (!TARGET_DECOMPOSE_LEA \
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&& INTEGRAL_MODE_P (GET_MODE (X)) \
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&& GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \
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{ \
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@ -2697,21 +2711,29 @@ do { \
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+ rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
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} \
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} \
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\
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/* fall through */ \
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\
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case MINUS: \
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if (FLOAT_MODE_P (GET_MODE (X))) \
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TOPLEVEL_COSTS_N_INSNS (ix86_cost->fadd); \
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/* fall through */ \
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\
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case AND: \
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case IOR: \
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case XOR: \
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case MINUS: \
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if (!TARGET_64BIT && GET_MODE (X) == DImode) \
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return (COSTS_N_INSNS (ix86_cost->add) * 2 \
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+ (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \
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<< (GET_MODE (XEXP (X, 0)) != DImode)) \
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+ (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \
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<< (GET_MODE (XEXP (X, 1)) != DImode))); \
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\
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/* fall through */ \
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\
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case NEG: \
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if (FLOAT_MODE_P (GET_MODE (X))) \
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TOPLEVEL_COSTS_N_INSNS (ix86_cost->fchs); \
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/* fall through */ \
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\
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case NOT: \
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if (!TARGET_64BIT && GET_MODE (X) == DImode) \
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TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
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@ -2723,6 +2745,16 @@ do { \
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TOPLEVEL_COSTS_N_INSNS (0); \
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break; \
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\
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case ABS: \
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if (FLOAT_MODE_P (GET_MODE (X))) \
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TOPLEVEL_COSTS_N_INSNS (ix86_cost->fabs); \
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break; \
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\
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case SQRT: \
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if (FLOAT_MODE_P (GET_MODE (X))) \
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TOPLEVEL_COSTS_N_INSNS (ix86_cost->fsqrt); \
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break; \
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\
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egress_rtx_costs: \
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break;
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