OpenE2K
/
gcc
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

mips.md (reload_outcc): Use HARD_REGNO_NREGS to access the second half of the TFmode scratch operand. 

* config/mips/mips.md (reload_outcc): Use HARD_REGNO_NREGS to
	access the second half of the TFmode scratch operand.

From-SVN: r44759
This commit is contained in:
Richard Sandiford 2001-08-10 13:01:31 +00:00 committed by Richard Sandiford
parent ca11a2e959
commit 2359d013c4
2 changed files with 12 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
gcc/ChangeLog
View File

@ -1,3 +1,8 @@
2001-08-10 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.md (reload_outcc): Use HARD_REGNO_NREGS to
access the second half of the TFmode scratch operand.
2001-08-10 Anthony Green <green@redhat.com>
* java/class.c (emit_register_classes): Conditionalize code on

9
gcc/config/mips/mips.md
View File

@ -5667,6 +5667,7 @@ move\\t%0,%z4\\n\\
{
rtx source;
rtx fp1, fp2;
int regno;
/* This is called when are copying some value into a condition code
register. Operand 0 is the condition code register. Operand 1
@ -5685,8 +5686,12 @@ move\\t%0,%z4\\n\\
else
source = operands[1];
fp1 = gen_rtx_REG (SFmode, REGNO (operands[2]));
fp2 = gen_rtx_REG (SFmode, REGNO (operands[2]) + 1);
/* FP1 and FP2 are the two halves of the TFmode scratch operand. They
will be single registers in 64-bit mode and register pairs in 32-bit
mode. SOURCE is loaded into FP1 and zero is loaded into FP2. */
regno = REGNO (operands[2]);
fp1 = gen_rtx_REG (SFmode, regno);
fp2 = gen_rtx_REG (SFmode, regno + HARD_REGNO_NREGS (regno, DFmode));
emit_insn (gen_move_insn (fp1, source));
emit_insn (gen_move_insn (fp2, gen_rtx_REG (SFmode, 0)));