aarch64-simd.md (aarch64_<su>mlal_lo<mode>): New pattern.
gcc/ChangeLog 2013-06-14 Vidya Praveen <vidyapraveen@arm.com> * config/aarch64/aarch64-simd.md (aarch64_<su>mlal_lo<mode>): New pattern. (aarch64_<su>mlal_hi<mode>, aarch64_<su>mlsl_lo<mode>): Likewise. (aarch64_<su>mlsl_hi<mode>, aarch64_<su>mlal<mode>): Likewise. (aarch64_<su>mlsl<mode>): Likewise. gcc/testsuite/ChangeLog 2013-06-14 Vidya Praveen <vidyapraveen@arm.com> * gcc.target/aarch64/vect_smlal_1.c: New file. From-SVN: r200096
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@ -1,3 +1,11 @@
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2013-06-14 Vidya Praveen <vidyapraveen@arm.com>
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* config/aarch64/aarch64-simd.md (aarch64_<su>mlal_lo<mode>):
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New pattern.
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(aarch64_<su>mlal_hi<mode>, aarch64_<su>mlsl_lo<mode>): Likewise.
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(aarch64_<su>mlsl_hi<mode>, aarch64_<su>mlal<mode>): Likewise.
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(aarch64_<su>mlsl<mode>): Likewise.
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2013-06-14 Mike Stump <mikestump@comcast.net>
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* Makefile.in (TARGET_H): Add insn-codes.h.
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@ -1190,6 +1190,104 @@
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;; Widening arithmetic.
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(define_insn "*aarch64_<su>mlal_lo<mode>"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(plus:<VWIDE>
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(mult:<VWIDE>
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(ANY_EXTEND:<VWIDE> (vec_select:<VHALF>
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(match_operand:VQW 2 "register_operand" "w")
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(match_operand:VQW 3 "vect_par_cnst_lo_half" "")))
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(ANY_EXTEND:<VWIDE> (vec_select:<VHALF>
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(match_operand:VQW 4 "register_operand" "w")
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(match_dup 3))))
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(match_operand:<VWIDE> 1 "register_operand" "0")))]
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"TARGET_SIMD"
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"<su>mlal\t%0.<Vwtype>, %2.<Vhalftype>, %4.<Vhalftype>"
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[(set_attr "simd_type" "simd_mlal")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_<su>mlal_hi<mode>"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(plus:<VWIDE>
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(mult:<VWIDE>
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(ANY_EXTEND:<VWIDE> (vec_select:<VHALF>
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(match_operand:VQW 2 "register_operand" "w")
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(match_operand:VQW 3 "vect_par_cnst_hi_half" "")))
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(ANY_EXTEND:<VWIDE> (vec_select:<VHALF>
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(match_operand:VQW 4 "register_operand" "w")
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(match_dup 3))))
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(match_operand:<VWIDE> 1 "register_operand" "0")))]
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"TARGET_SIMD"
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"<su>mlal2\t%0.<Vwtype>, %2.<Vtype>, %4.<Vtype>"
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[(set_attr "simd_type" "simd_mlal")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_<su>mlsl_lo<mode>"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(minus:<VWIDE>
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(match_operand:<VWIDE> 1 "register_operand" "0")
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(mult:<VWIDE>
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(ANY_EXTEND:<VWIDE> (vec_select:<VHALF>
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(match_operand:VQW 2 "register_operand" "w")
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(match_operand:VQW 3 "vect_par_cnst_lo_half" "")))
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(ANY_EXTEND:<VWIDE> (vec_select:<VHALF>
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(match_operand:VQW 4 "register_operand" "w")
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(match_dup 3))))))]
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"TARGET_SIMD"
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"<su>mlsl\t%0.<Vwtype>, %2.<Vhalftype>, %4.<Vhalftype>"
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[(set_attr "simd_type" "simd_mlal")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_<su>mlsl_hi<mode>"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(minus:<VWIDE>
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(match_operand:<VWIDE> 1 "register_operand" "0")
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(mult:<VWIDE>
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(ANY_EXTEND:<VWIDE> (vec_select:<VHALF>
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(match_operand:VQW 2 "register_operand" "w")
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(match_operand:VQW 3 "vect_par_cnst_hi_half" "")))
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(ANY_EXTEND:<VWIDE> (vec_select:<VHALF>
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(match_operand:VQW 4 "register_operand" "w")
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(match_dup 3))))))]
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"TARGET_SIMD"
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"<su>mlsl2\t%0.<Vwtype>, %2.<Vtype>, %4.<Vtype>"
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[(set_attr "simd_type" "simd_mlal")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_<su>mlal<mode>"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(plus:<VWIDE>
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(mult:<VWIDE>
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(ANY_EXTEND:<VWIDE>
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(match_operand:VDW 1 "register_operand" "w"))
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(ANY_EXTEND:<VWIDE>
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(match_operand:VDW 2 "register_operand" "w")))
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(match_operand:<VWIDE> 3 "register_operand" "0")))]
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"TARGET_SIMD"
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"<su>mlal\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
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[(set_attr "simd_type" "simd_mlal")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_<su>mlsl<mode>"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(minus:<VWIDE>
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(match_operand:<VWIDE> 1 "register_operand" "0")
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(mult:<VWIDE>
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(ANY_EXTEND:<VWIDE>
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(match_operand:VDW 2 "register_operand" "w"))
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(ANY_EXTEND:<VWIDE>
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(match_operand:VDW 3 "register_operand" "w")))))]
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"TARGET_SIMD"
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"<su>mlsl\t%0.<Vwtype>, %2.<Vtype>, %3.<Vtype>"
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[(set_attr "simd_type" "simd_mlal")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "aarch64_simd_vec_<su>mult_lo_<mode>"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(mult:<VWIDE> (ANY_EXTEND:<VWIDE> (vec_select:<VHALF>
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@ -1,3 +1,7 @@
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2013-06-14 Vidya Praveen <vidyapraveen@arm.com>
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* gcc.target/aarch64/vect_smlal_1.c: New file.
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2013-06-14 Tobias Burnus <burnus@net-b.de>
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PR fortran/57508
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325
gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c
Normal file
325
gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c
Normal file
@ -0,0 +1,325 @@
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/* { dg-do run } */
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/* { dg-options "-O3 -fno-inline -save-temps -fno-vect-cost-model" } */
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typedef signed char S8_t;
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typedef signed short S16_t;
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typedef signed int S32_t;
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typedef signed long S64_t;
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typedef signed char *__restrict__ pS8_t;
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typedef signed short *__restrict__ pS16_t;
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typedef signed int *__restrict__ pS32_t;
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typedef signed long *__restrict__ pS64_t;
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typedef unsigned char U8_t;
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typedef unsigned short U16_t;
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typedef unsigned int U32_t;
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typedef unsigned long U64_t;
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typedef unsigned char *__restrict__ pU8_t;
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typedef unsigned short *__restrict__ pU16_t;
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typedef unsigned int *__restrict__ pU32_t;
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typedef unsigned long *__restrict__ pU64_t;
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extern void abort ();
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void
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test_addS64_tS32_t4 (pS64_t a, pS32_t b, pS32_t c)
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{
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int i;
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for (i = 0; i < 4; i++)
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a[i] += (S64_t) b[i] * (S64_t) c[i];
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}
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/* { dg-final { scan-assembler "smlal\tv\[0-9\]+\.2d" } } */
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/* { dg-final { scan-assembler "smlal2\tv\[0-9\]+\.2d" } } */
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void
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test_addS32_tS16_t8 (pS32_t a, pS16_t b, pS16_t c)
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{
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int i;
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for (i = 0; i < 8; i++)
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a[i] += (S32_t) b[i] * (S32_t) c[i];
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}
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/* { dg-final { scan-assembler "smlal\tv\[0-9\]+\.4s" } } */
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/* { dg-final { scan-assembler "smlal2\tv\[0-9\]+\.4s" } } */
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void
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test_addS16_tS8_t16 (pS16_t a, pS8_t b, pS8_t c)
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{
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int i;
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for (i = 0; i < 16; i++)
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a[i] += (S16_t) b[i] * (S16_t) c[i];
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}
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void
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test_addS16_tS8_t16_neg0 (pS16_t a, pS8_t b, pS8_t c)
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{
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int i;
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for (i = 0; i < 16; i++)
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a[i] += (S16_t) -b[i] * (S16_t) -c[i];
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}
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void
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test_addS16_tS8_t16_neg1 (pS16_t a, pS8_t b, pS8_t c)
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{
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int i;
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for (i = 0; i < 16; i++)
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a[i] -= (S16_t) b[i] * (S16_t) -c[i];
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}
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void
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test_addS16_tS8_t16_neg2 (pS16_t a, pS8_t b, pS8_t c)
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{
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int i;
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for (i = 0; i < 16; i++)
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a[i] -= (S16_t) -b[i] * (S16_t) c[i];
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}
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/* { dg-final { scan-assembler-times "smlal\tv\[0-9\]+\.8h" 4 } } */
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/* { dg-final { scan-assembler-times "smlal2\tv\[0-9\]+\.8h" 4 } } */
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void
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test_subS64_tS32_t4 (pS64_t a, pS32_t b, pS32_t c)
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{
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int i;
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for (i = 0; i < 4; i++)
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a[i] -= (S64_t) b[i] * (S64_t) c[i];
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}
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/* { dg-final { scan-assembler "smlsl\tv\[0-9\]+\.2d" } } */
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/* { dg-final { scan-assembler "smlsl2\tv\[0-9\]+\.2d" } } */
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void
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test_subS32_tS16_t8 (pS32_t a, pS16_t b, pS16_t c)
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{
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int i;
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for (i = 0; i < 8; i++)
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a[i] -= (S32_t) b[i] * (S32_t) c[i];
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}
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/* { dg-final { scan-assembler "smlsl\tv\[0-9\]+\.4s" } } */
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/* { dg-final { scan-assembler "smlsl2\tv\[0-9\]+\.4s" } } */
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void
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test_subS16_tS8_t16 (pS16_t a, pS8_t b, pS8_t c)
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{
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int i;
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for (i = 0; i < 16; i++)
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a[i] -= (S16_t) b[i] * (S16_t) c[i];
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}
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void
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test_subS16_tS8_t16_neg0 (pS16_t a, pS8_t b, pS8_t c)
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{
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int i;
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for (i = 0; i < 16; i++)
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a[i] += (S16_t) -b[i] * (S16_t) c[i];
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}
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void
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test_subS16_tS8_t16_neg1 (pS16_t a, pS8_t b, pS8_t c)
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{
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int i;
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for (i = 0; i < 16; i++)
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a[i] += (S16_t) b[i] * (S16_t) -c[i];
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}
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void
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test_subS16_tS8_t16_neg2 (pS16_t a, pS8_t b, pS8_t c)
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{
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int i;
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for (i = 0; i < 16; i++)
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a[i] += -((S16_t) b[i] * (S16_t) c[i]);
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}
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void
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test_subS16_tS8_t16_neg3 (pS16_t a, pS8_t b, pS8_t c)
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{
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int i;
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for (i = 0; i < 16; i++)
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a[i] -= (S16_t) -b[i] * (S16_t) -c[i];
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}
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/* { dg-final { scan-assembler-times "smlsl\tv\[0-9\]+\.8h" 5 } } */
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/* { dg-final { scan-assembler-times "smlsl2\tv\[0-9\]+\.8h" 5 } } */
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void
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test_addU64_tU32_t4 (pU64_t a, pU32_t b, pU32_t c)
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{
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int i;
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for (i = 0; i < 4; i++)
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a[i] += (U64_t) b[i] * (U64_t) c[i];
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}
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/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.2d" } } */
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/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.2d" } } */
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void
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test_addU32_tU16_t8 (pU32_t a, pU16_t b, pU16_t c)
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{
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int i;
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for (i = 0; i < 8; i++)
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a[i] += (U32_t) b[i] * (U32_t) c[i];
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}
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/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.4s" } } */
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/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.4s" } } */
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void
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test_addU16_tU8_t16 (pU16_t a, pU8_t b, pU8_t c)
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{
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int i;
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for (i = 0; i < 16; i++)
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a[i] += (U16_t) b[i] * (U16_t) c[i];
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}
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/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.8h" } } */
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/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.8h" } } */
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void
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test_subU64_tU32_t4 (pU64_t a, pU32_t b, pU32_t c)
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{
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int i;
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for (i = 0; i < 4; i++)
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a[i] -= (U64_t) b[i] * (U64_t) c[i];
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}
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/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.2d" } } */
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/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.2d" } } */
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void
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test_subU32_tU16_t8 (pU32_t a, pU16_t b, pU16_t c)
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{
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int i;
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for (i = 0; i < 8; i++)
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a[i] -= (U32_t) b[i] * (U32_t) c[i];
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}
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/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.4s" } } */
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/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.4s" } } */
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void
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test_subU16_tU8_t16 (pU16_t a, pU8_t b, pU8_t c)
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{
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int i;
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for (i = 0; i < 16; i++)
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a[i] -= (U16_t) b[i] * (U16_t) c[i];
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}
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/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.8h" } } */
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/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.8h" } } */
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S64_t add_rS64[4] = { 6, 7, -4, -3 };
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S32_t add_rS32[8] = { 6, 7, -4, -3, 10, 11, 0, 1 };
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S16_t add_rS16[16] =
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{ 6, 7, -4, -3, 10, 11, 0, 1, 14, 15, 4, 5, 18, 19, 8, 9 };
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S64_t sub_rS64[4] = { 0, 1, 2, 3 };
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S32_t sub_rS32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
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S16_t sub_rS16[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
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U64_t add_rU64[4] = { 0x6, 0x7, 0x2fffffffc, 0x2fffffffd };
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U32_t add_rU32[8] =
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{
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0x6, 0x7, 0x2fffc, 0x2fffd,
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0xa, 0xb, 0x30000, 0x30001
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};
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U16_t add_rU16[16] =
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{
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0x6, 0x7, 0x2fc, 0x2fd, 0xa, 0xb, 0x300, 0x301,
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0xe, 0xf, 0x304, 0x305, 0x12, 0x13, 0x308, 0x309
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};
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U64_t sub_rU64[4] = { 0, 1, 2, 3 };
|
||||
U32_t sub_rU32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
|
||||
U16_t sub_rU16[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
|
||||
|
||||
S8_t neg_r[16] = { -6, -5, 8, 9, -2, -1, 12, 13, 2, 3, 16, 17, 6, 7, 20, 21 };
|
||||
|
||||
S64_t S64_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
|
||||
S32_t S32_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 };
|
||||
S32_t S32_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 };
|
||||
|
||||
S32_t S32_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
|
||||
S16_t S16_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 };
|
||||
S16_t S16_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 };
|
||||
|
||||
S16_t S16_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
|
||||
S8_t S8_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 };
|
||||
S8_t S8_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 };
|
||||
|
||||
|
||||
#define CHECK(T,N,AS,US) \
|
||||
do \
|
||||
{ \
|
||||
for (i = 0; i < N; i++) \
|
||||
if (S##T##_ta[i] != AS##_r##US##T[i]) \
|
||||
abort (); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
#define SCHECK(T,N,AS) CHECK(T,N,AS,S)
|
||||
#define UCHECK(T,N,AS) CHECK(T,N,AS,U)
|
||||
|
||||
#define NCHECK(RES) \
|
||||
do \
|
||||
{ \
|
||||
for (i = 0; i < 16; i++) \
|
||||
if (S16_ta[i] != RES[i]) \
|
||||
abort (); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
|
||||
int
|
||||
main ()
|
||||
{
|
||||
int i;
|
||||
|
||||
test_addS64_tS32_t4 (S64_ta, S32_tb, S32_tc);
|
||||
SCHECK (64, 4, add);
|
||||
test_addS32_tS16_t8 (S32_ta, S16_tb, S16_tc);
|
||||
SCHECK (32, 8, add);
|
||||
test_addS16_tS8_t16 (S16_ta, S8_tb, S8_tc);
|
||||
SCHECK (16, 16, add);
|
||||
test_subS64_tS32_t4 (S64_ta, S32_tb, S32_tc);
|
||||
SCHECK (64, 4, sub);
|
||||
test_subS32_tS16_t8 (S32_ta, S16_tb, S16_tc);
|
||||
SCHECK (32, 8, sub);
|
||||
test_subS16_tS8_t16 (S16_ta, S8_tb, S8_tc);
|
||||
SCHECK (16, 16, sub);
|
||||
|
||||
test_addU64_tU32_t4 (S64_ta, S32_tb, S32_tc);
|
||||
UCHECK (64, 4, add);
|
||||
test_addU32_tU16_t8 (S32_ta, S16_tb, S16_tc);
|
||||
UCHECK (32, 8, add);
|
||||
test_addU16_tU8_t16 (S16_ta, S8_tb, S8_tc);
|
||||
UCHECK (16, 16, add);
|
||||
test_subU64_tU32_t4 (S64_ta, S32_tb, S32_tc);
|
||||
UCHECK (64, 4, sub);
|
||||
test_subU32_tU16_t8 (S32_ta, S16_tb, S16_tc);
|
||||
UCHECK (32, 8, sub);
|
||||
test_subU16_tU8_t16 (S16_ta, S8_tb, S8_tc);
|
||||
UCHECK (16, 16, sub);
|
||||
|
||||
test_addS16_tS8_t16_neg0 (S16_ta, S8_tb, S8_tc);
|
||||
NCHECK (add_rS16);
|
||||
test_subS16_tS8_t16_neg0 (S16_ta, S8_tb, S8_tc);
|
||||
NCHECK (sub_rS16);
|
||||
test_addS16_tS8_t16_neg1 (S16_ta, S8_tb, S8_tc);
|
||||
NCHECK (add_rS16);
|
||||
test_subS16_tS8_t16_neg1 (S16_ta, S8_tb, S8_tc);
|
||||
NCHECK (sub_rS16);
|
||||
test_addS16_tS8_t16_neg2 (S16_ta, S8_tb, S8_tc);
|
||||
NCHECK (add_rS16);
|
||||
test_subS16_tS8_t16_neg2 (S16_ta, S8_tb, S8_tc);
|
||||
NCHECK (sub_rS16);
|
||||
test_subS16_tS8_t16_neg3 (S16_ta, S8_tb, S8_tc);
|
||||
NCHECK (neg_r);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
Loading…
x
Reference in New Issue
Block a user