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Output vextract{i,f}{32x4,64x2} for (vec_select:(reg:Vmode) idx) when byte_offset of idx % 16 == 0. 

2020-09-13  Hongtao Liu  <hongtao.liu@intel.com>
	    Peter Cordes  <peter@cordes.ca>
gcc/ChangeLog:

	PR target/91103
	* config/i386/sse.md (extract_suf): Add V8SF/V8SI/V4DF/V4DI.
	(*vec_extract<mode><ssescalarmodelower>_valign): Output
	vextract{i,f}{32x4,64x2} instruction when byte_offset % 16 ==
	0.

gcc/testsuite/ChangeLog:

	PR target/91103
	* gcc.target/i386/pr91103-1.c: Add extract tests.
	* gcc.target/i386/pr91103-2.c: Ditto.
This commit is contained in:
liuhongt 2021-09-13 10:27:51 +08:00
parent 8b69c481fc
commit 243e0a5b19
3 changed files with 27 additions and 5 deletions
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21
gcc/config/i386/sse.md
View File

@ -9089,7 +9089,8 @@
[(V16SF "avx512f") (V16SI "avx512f") (V8DF "avx512dq") (V8DI "avx512dq")])
(define_mode_attr extract_suf
[(V16SF "32x4") (V16SI "32x4") (V8DF "64x2") (V8DI "64x2")])
[(V16SF "32x4") (V16SI "32x4") (V8DF "64x2") (V8DI "64x2")
(V8SF "32x4") (V8SI "32x4") (V4DF "64x2") (V4DI "64x2")])
(define_mode_iterator AVX512_VEC
[(V8DF "TARGET_AVX512DQ") (V8DI "TARGET_AVX512DQ") V16SF V16SI])
@ -10661,9 +10662,21 @@
(match_operand:V48_256_512_AVX512VL 1 "register_operand" "v")
(parallel [(match_operand 2 "<vec_extract_imm_predicate>")])))]
"TARGET_AVX512F
&& INTVAL(operands[2]) >= 16 / GET_MODE_SIZE (<ssescalarmode>mode)"
"valign<ternlogsuffix>\t{%2, %1, %1, %<xtg_mode>0|%<xtg_mode>0, %1, %1, %2}";
[(set_attr "prefix" "evex")
&& INTVAL(operands[2]) * GET_MODE_SIZE (<ssescalarmode>mode) >= 16"
{
int byte_offset = INTVAL (operands[2]) * GET_MODE_SIZE (<ssescalarmode>mode);
if (byte_offset % 16 == 0)
{
operands[2] = GEN_INT (byte_offset / 16);
if (byte_offset / 16 == 1)
return "vextract<shuffletype><extract_suf>\t{%2, %t1, %x0|%x0, %t1, %2}";
else
return "vextract<shuffletype><extract_suf>\t{%2, %1, %x0|%x0, %1, %2}";
}
else
return "valign<ternlogsuffix>\t{%2, %1, %1, %<xtg_mode>0|%<xtg_mode>0, %1, %1, %2}";
}
[(set_attr "prefix" "maybe_evex")
(set_attr "mode" "<sseintvecinsnmode>")])
(define_expand "avx512f_shufps512_mask"

7
gcc/testsuite/gcc.target/i386/pr91103-1.c
View File

@ -1,6 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-mavx512vl -O2" } */
/* { dg-final { scan-assembler-times "valign\[dq\]" 16 } } */
/* { dg-final { scan-assembler-times "valign\[dq\]" 8 } } */
/* { dg-final { scan-assembler-times "vextract" 12 } } */
typedef float v8sf __attribute__((vector_size(32)));
typedef float v16sf __attribute__((vector_size(64)));
@ -23,9 +24,13 @@ EXTRACT (v8sf, float, 4);
EXTRACT (v8sf, float, 7);
EXTRACT (v8si, int, 4);
EXTRACT (v8si, int, 7);
EXTRACT (v16sf, float, 4);
EXTRACT (v16sf, float, 8);
EXTRACT (v16sf, float, 12);
EXTRACT (v16sf, float, 15);
EXTRACT (v16si, int, 4);
EXTRACT (v16si, int, 8);
EXTRACT (v16si, int, 12);
EXTRACT (v16si, int, 15);
EXTRACT (v4df, double, 2);
EXTRACT (v4df, double, 3);

4
gcc/testsuite/gcc.target/i386/pr91103-2.c
View File

@ -61,9 +61,13 @@ RUNCHECK (f2, v8sf, float, 4);
RUNCHECK (f2, v8sf, float, 7);
RUNCHECK (di2, v8si, int, 4);
RUNCHECK (di2, v8si, int, 7);
RUNCHECK (f1, v16sf, float, 4);
RUNCHECK (f1, v16sf, float, 8);
RUNCHECK (f1, v16sf, float, 12);
RUNCHECK (f1, v16sf, float, 15);
RUNCHECK (di1, v16si, int, 4);
RUNCHECK (di1, v16si, int, 8);
RUNCHECK (di1, v16si, int, 12);
RUNCHECK (di1, v16si, int, 15);
RUNCHECK (d2, v4df, double, 2);
RUNCHECK (d2, v4df, double, 3);