re PR target/6362 (mips-irix6 gcc-3.1 C testsuite failure with -mips4 in compile/920501-4.c)
* mips.h (FP_INC): Define. Backport fix for PR6362: 2002-10-01 Richard Sandiford <rsandifo@redhat.com> * config/mips/mips-protos.h (mips_emit_fcc_reload): Declare. * config/mips/mips.h (PREDICATE_CODES): Add fcc_register_operand. * config/mips/mips.c (fcc_register_operand): New function. (mips_emit_fcc_reload): New function, extracted from reload_incc. * cnfig/mips/mips.md (reload_incc): Change destination prediate to fcc_register_operand. Remove misleading source constraint. Use mips_emit_fcc_reload. (reload_outcc): Duplicate reload_incc. From-SVN: r62770
This commit is contained in:
Kaveh R. Ghazi
Kaveh Ghazi
parent
a9802526ea
commit
243f24b4c7
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@ -1,3 +1,19 @@
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2003-02-12 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
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* mips.h (FP_INC): Define.
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Backport fix for PR6362:
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2002-10-01 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips-protos.h (mips_emit_fcc_reload): Declare.
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* config/mips/mips.h (PREDICATE_CODES): Add fcc_register_operand.
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* config/mips/mips.c (fcc_register_operand): New function.
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(mips_emit_fcc_reload): New function, extracted from reload_incc.
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* cnfig/mips/mips.md (reload_incc): Change destination prediate
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to fcc_register_operand. Remove misleading source constraint.
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Use mips_emit_fcc_reload.
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(reload_outcc): Duplicate reload_incc.
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2003-02-11 Bob Wilson <bob.wilson@acm.org>
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Backport following patch:
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@ -80,6 +80,7 @@ extern void init_cumulative_args PARAMS ((CUMULATIVE_ARGS *,
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tree, rtx));
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extern void gen_conditional_move PARAMS ((rtx *));
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extern void mips_gen_conditional_trap PARAMS ((rtx *));
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extern void mips_emit_fcc_reload PARAMS ((rtx, rtx, rtx));
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extern void machine_dependent_reorg PARAMS ((rtx));
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extern int mips_address_cost PARAMS ((rtx));
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extern void mips_count_memory_refs PARAMS ((rtx, int));
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@ -3267,6 +3267,51 @@ mips_gen_conditional_trap (operands)
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gen_rtx (cmp_code, GET_MODE (operands[0]), op0, op1),
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operands[1]));
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}
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/* Return true if operand OP is a condition code register.
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Only for use during or after reload. */
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int
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fcc_register_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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return ((mode == VOIDmode || mode == GET_MODE (op))
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&& (reload_in_progress || reload_completed)
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&& (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
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&& ST_REG_P (true_regnum (op)));
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}
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/* Emit code to move general operand SRC into condition-code
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register DEST. SCRATCH is a scratch TFmode float register.
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The sequence is:
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FP1 = SRC
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FP2 = 0.0f
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DEST = FP2 < FP1
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where FP1 and FP2 are single-precision float registers
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taken from SCRATCH. */
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void
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mips_emit_fcc_reload (dest, src, scratch)
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rtx dest, src, scratch;
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{
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rtx fp1, fp2;
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/* Change the source to SFmode. */
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if (GET_CODE (src) == MEM)
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src = adjust_address (src, SFmode, 0);
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else if (GET_CODE (src) == REG || GET_CODE (src) == SUBREG)
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src = gen_rtx_REG (SFmode, true_regnum (src));
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fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
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fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
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emit_move_insn (copy_rtx (fp1), src);
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emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
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emit_insn (gen_slt_sf (dest, fp2, fp1));
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}
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/* Write a loop to move a constant number of bytes.
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Generate load/stores as follows:
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@ -1582,6 +1582,10 @@ do { \
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/* For MIPS, width of a floating point register. */
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#define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
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/* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
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the next available register. */
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#define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
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/* A C expression for the size in bits of the type `int' on the
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target machine. If you don't define this, the default is one
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word. */
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@ -4001,6 +4005,7 @@ while (0)
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{"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
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{"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
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CONST_DOUBLE, CONST }}, \
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{"fcc_register_operand", { REG, SUBREG }}, \
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{"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
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{"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
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@ -5786,77 +5786,39 @@ move\\t%0,%z4\\n\\
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(set_attr "mode" "SI")
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(set_attr "length" "8,4,4,8,4,8,4,4,4,4,8,4,8")])
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;; Reload condition code registers. These need scratch registers.
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;; Reload condition code registers. reload_incc and reload_outcc
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;; both handle moves from arbitrary operands into condition code
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;; registers. reload_incc handles the more common case in which
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;; a source operand is constrained to be in a condition-code
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;; register, but has not been allocated to one.
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;;
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;; Sometimes, such as in movcc, we have a CCmode destination whose
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;; constraints do not include 'z'. reload_outcc handles the case
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;; when such an operand is allocated to a condition-code register.
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;;
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;; Note that reloads from a condition code register to some
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;; other location can be done using ordinary moves. Moving
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;; into a GPR takes a single movcc, moving elsewhere takes
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;; two. We can leave these cases to the generic reload code.
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(define_expand "reload_incc"
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[(set (match_operand:CC 0 "register_operand" "=z")
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(match_operand:CC 1 "general_operand" "z"))
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[(set (match_operand:CC 0 "fcc_register_operand" "=z")
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(match_operand:CC 1 "general_operand" ""))
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(clobber (match_operand:TF 2 "register_operand" "=&f"))]
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"ISA_HAS_8CC && TARGET_HARD_FLOAT"
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"
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{
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rtx source;
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rtx fp1, fp2;
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int regno;
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/* This is called when are copying some value into a condition code
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register. Operand 0 is the condition code register. Operand 1
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is the source. Operand 2 is a scratch register; we use TFmode
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because we actually need two floating point registers. */
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if (! ST_REG_P (true_regnum (operands[0]))
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|| ! FP_REG_P (true_regnum (operands[2])))
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abort ();
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/* We need to get the source in SFmode so that the insn is
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recognized. */
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if (GET_CODE (operands[1]) == MEM)
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source = adjust_address (operands[1], SFmode, 0);
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else if (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG)
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source = gen_rtx_REG (SFmode, true_regnum (operands[1]));
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else
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source = operands[1];
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/* FP1 and FP2 are the two halves of the TFmode scratch operand. They
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will be single registers in 64-bit mode and register pairs in 32-bit
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mode. SOURCE is loaded into FP1 and zero is loaded into FP2. */
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regno = REGNO (operands[2]);
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fp1 = gen_rtx_REG (SFmode, regno);
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fp2 = gen_rtx_REG (SFmode, regno + HARD_REGNO_NREGS (regno, DFmode));
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emit_insn (gen_move_insn (fp1, source));
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emit_insn (gen_move_insn (fp2, gen_rtx_REG (SFmode, 0)));
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emit_insn (gen_rtx_SET (VOIDmode, operands[0],
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gen_rtx_LT (CCmode, fp2, fp1)));
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mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
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DONE;
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}")
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(define_expand "reload_outcc"
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[(set (match_operand:CC 0 "general_operand" "=z")
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(match_operand:CC 1 "register_operand" "z"))
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(clobber (match_operand:CC 2 "register_operand" "=&d"))]
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[(set (match_operand:CC 0 "fcc_register_operand" "=z")
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(match_operand:CC 1 "register_operand" ""))
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(clobber (match_operand:TF 2 "register_operand" "=&f"))]
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"ISA_HAS_8CC && TARGET_HARD_FLOAT"
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"
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{
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/* This is called when we are copying a condition code register out
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to save it somewhere. Operand 0 should be the location we are
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going to save it to. Operand 1 should be the condition code
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register. Operand 2 should be a scratch general purpose register
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created for us by reload. The mips_secondary_reload_class
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function should have told reload that we don't need a scratch
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register if the destination is a general purpose register anyhow. */
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if (ST_REG_P (true_regnum (operands[0]))
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|| GP_REG_P (true_regnum (operands[0]))
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|| ! ST_REG_P (true_regnum (operands[1]))
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|| ! GP_REG_P (true_regnum (operands[2])))
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abort ();
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/* All we have to do is copy the value from the condition code to
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the data register, which movcc can handle, and then store the
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value into the real final destination. */
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emit_insn (gen_move_insn (operands[2], operands[1]));
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emit_insn (gen_move_insn (operands[0], operands[2]));
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mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
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DONE;
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}")
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