aarch64: Fix ICE when expanding scalar floating move with -mgeneral-regs-only. [PR94991]
In the testcase for PR94991, we are doing FAIL for scalar floating move expand pattern since TARGET_FLOAT is false with option -mgeneral-regs-only. But move expand pattern cannot fail. It would be better to replace the FAIL with code that bitcasts to the equivalent integer mode using gen_lowpart. 2020-05-11 Felix Yang <felix.yang@huawei.com> gcc/ PR target/94991 * config/aarch64/aarch64.md (mov<mode>): Bitcasts to the equivalent integer mode using gen_lowpart instead of doing FAIL for scalar floating point move. gcc/testsuite/ PR target/94991 * gcc.target/aarch64/mgeneral-regs_5.c: New test.
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2020-05-11 Felix Yang <felix.yang@huawei.com>
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PR target/94991
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* config/aarch64/aarch64.md (mov<mode>):
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Bitcasts to the equivalent integer mode using gen_lowpart
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instead of doing FAIL for scalar floating point move.
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2020-05-11 Alex Coplan <alex.coplan@arm.com>
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* config/aarch64/aarch64.c (aarch64_if_then_else_costs): Add case
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@ -1364,7 +1364,11 @@
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if (!TARGET_FLOAT)
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{
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aarch64_err_no_fpadvsimd (<MODE>mode);
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FAIL;
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machine_mode intmode
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= int_mode_for_size (GET_MODE_BITSIZE (<MODE>mode), 0).require ();
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emit_move_insn (gen_lowpart (intmode, operands[0]),
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gen_lowpart (intmode, operands[1]));
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DONE;
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}
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if (GET_CODE (operands[0]) == MEM
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@ -1,3 +1,8 @@
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2020-05-11 Felix Yang <felix.yang@huawei.com>
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PR target/94991
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* gcc.target/aarch64/mgeneral-regs_5.c: New test.
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2020-05-11 Alex Coplan <alex.coplan@arm.com>
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* gcc.target/aarch64/csinv-neg.c: New test.
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/* { dg-options "-mgeneral-regs-only -O2" } */
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struct S { float d; };
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void bar (struct S);
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void
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f0 (int x)
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{
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struct S s = { .d = 0.0f }; /* { dg-error "'-mgeneral-regs-only' is incompatible with the use of floating-point types" } */
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((char *) &s.d)[0] = x;
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s.d *= 7.0; /* { dg-error "'-mgeneral-regs-only' is incompatible with the use of floating-point types" } */
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bar (s); /* { dg-error "'-mgeneral-regs-only' is incompatible with the use of floating-point types" } */
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}
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