Revert unapproved changes that were inadvertanly brought in with the previous
delta. From-SVN: r32608
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665f250366
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24994dd5d7
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@ -250,22 +250,6 @@ Unrecognized value in TARGET_CPU_DEFAULT.
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#define SUBTARGET_CPP_SPEC ""
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#endif
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#ifndef SUBTARGET_EXTRA_ASM_SPEC
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#define SUBTARGET_EXTRA_ASM_SPEC
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#endif
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#ifndef ASM_SPEC
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#define ASM_SPEC "\
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%{mbig-endian:-EB} \
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%{mcpu=*:-m%*} \
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%{march=*:-m%*} \
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%{mapcs-*:-mapcs-%*} \
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%{matpcs:-matpcs} \
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%{mapcs-float:-mfloat} \
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%{msoft-float:-mno-fpu} \
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%{mthumb-interwork:-mthumb-interwork} \
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" SUBTARGET_EXTRA_ASM_SPEC
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#endif
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/* Run-time Target Specification. */
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#ifndef TARGET_VERSION
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@ -337,15 +321,6 @@ Unrecognized value in TARGET_CPU_DEFAULT.
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/* Nonzero if all call instructions should be indirect. */
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#define ARM_FLAG_LONG_CALLS (1 << 15)
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/* Set if ATPCS compliance is required. Note there *are* some
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incompatabilities between APCS and ATPCS. */
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#define ARM_FLAG_ATPCS (1 << 16)
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/* Set if compatability with older versions of GCC is required,
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where struct { float a; } would be returned from a function
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by a hidden extra argument rather than in r0. */
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#define ARM_FLAG_BUGGY_RETURN_IN_MEMORY (1 << 17)
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#define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME)
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#define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
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#define TARGET_FPE (target_flags & ARM_FLAG_FPE)
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@ -363,8 +338,6 @@ Unrecognized value in TARGET_CPU_DEFAULT.
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#define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
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#define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
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#define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
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#define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS)
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#define TARGET_BUGGY_RETURN_IN_MEMORY (target_flags & ARM_FLAG_BUGGY_RETURN_IN_MEMORY)
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/* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
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Bit 31 is reserved. See riscix.h. */
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@ -426,12 +399,6 @@ Unrecognized value in TARGET_CPU_DEFAULT.
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{"long-calls", ARM_FLAG_LONG_CALLS, \
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"Generate call insns as indirect calls, if necessary"}, \
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{"no-long-calls", -ARM_FLAG_LONG_CALLS, ""}, \
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{"atpcs", ARM_FLAG_ATPCS, \
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"generate ATPCS compliant code, rather than APCS compliant code" }, \
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{"no-atpcs", -ARM_FLAG_ATPCS, "" }, \
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{"buggy-return-in-memory", ARM_FLAG_BUGGY_RETURN_IN_MEMORY,\
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"return struct { float a; } in memory" }, \
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{"no-buggy-return-in-memory",-ARM_FLAG_BUGGY_RETURN_IN_MEMORY, "" }, \
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SUBTARGET_SWITCHES \
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{"", TARGET_DEFAULT, "" } \
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}
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@ -2011,10 +1978,6 @@ extern int making_const_table;
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/* Handle pragmas for compatibility with Intel's compilers. */
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#define HANDLE_PRAGMA(GET, UNGET, NAME) arm_process_pragma (GET, UNGET, NAME)
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/* Allow short-call attribute functions to be inlined. */
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#define FUNCTION_ATTRIBUTE_INLINABLE_P(fndecl) \
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arm_function_attribute_inlineable_p (fndecl);
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/* Condition code information. */
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/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
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