[amdgcn] Update CFI configuration
Currently we don't get any call frame information for the amdgcn target. This patch makes necessary adjustments to generate CFI that can work with ROCGDB (ROCm 3.8+). gcc/ * config/gcn/gcn.c (move_callee_saved_registers): Emit CFI notes for prologue register saves. (gcn_debug_unwind_info): Use UI_DWARF2. (gcn_dwarf_register_number): Map DWARF_LINK_REGISTER to DWARF PC. (gcn_dwarf_register_span): DWARF_LINK_REGISTER doesn't span. * config/gcn/gcn.h: (DWARF_FRAME_RETURN_COLUMN): New define. (DWARF_LINK_REGISTER): New define. (FIRST_PSEUDO_REGISTER): Increment. (FIXED_REGISTERS): Add entry for DWARF_LINK_REGISTER. (CALL_USED_REGISTERS): Likewise. (REGISTER_NAMES): Likewise.
This commit is contained in:
Hafiz Abid Qadeer
parent
e66d0b7b87
commit
251697a64b
@ -2649,6 +2649,7 @@ move_callee_saved_registers (rtx sp, machine_function *offsets,
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rtx as = gen_rtx_CONST_INT (VOIDmode, STACK_ADDR_SPACE);
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HOST_WIDE_INT exec_set = 0;
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int offreg_set = 0;
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auto_vec<int> saved_sgprs;
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start_sequence ();
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@ -2665,7 +2666,10 @@ move_callee_saved_registers (rtx sp, machine_function *offsets,
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int lane = saved_scalars % 64;
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if (prologue)
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emit_insn (gen_vec_setv64si (vreg, reg, GEN_INT (lane)));
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{
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emit_insn (gen_vec_setv64si (vreg, reg, GEN_INT (lane)));
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saved_sgprs.safe_push (regno);
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}
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else
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emit_insn (gen_vec_extractv64sisi (reg, vreg, GEN_INT (lane)));
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@ -2698,7 +2702,7 @@ move_callee_saved_registers (rtx sp, machine_function *offsets,
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gcn_gen_undef (V64SImode), exec));
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/* Move vectors. */
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for (regno = FIRST_VGPR_REG, offset = offsets->pretend_size;
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for (regno = FIRST_VGPR_REG, offset = 0;
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regno < FIRST_PSEUDO_REGISTER; regno++)
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if ((df_regs_ever_live_p (regno) && !call_used_or_fixed_reg_p (regno))
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|| (regno == VGPR_REGNO (6) && saved_scalars > 0)
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@ -2719,8 +2723,67 @@ move_callee_saved_registers (rtx sp, machine_function *offsets,
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}
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if (prologue)
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emit_insn (gen_scatterv64si_insn_1offset_exec (vsp, const0_rtx, reg,
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as, const0_rtx, exec));
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{
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rtx insn = emit_insn (gen_scatterv64si_insn_1offset_exec
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(vsp, const0_rtx, reg, as, const0_rtx,
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exec));
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/* Add CFI metadata. */
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rtx note;
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if (regno == VGPR_REGNO (6) || regno == VGPR_REGNO (7))
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{
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int start = (regno == VGPR_REGNO (7) ? 64 : 0);
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int count = MIN (saved_scalars - start, 64);
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int add_lr = (regno == VGPR_REGNO (6)
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&& df_regs_ever_live_p (LINK_REGNUM));
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int lrdest = -1;
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rtvec seq = rtvec_alloc (count + add_lr);
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/* Add an REG_FRAME_RELATED_EXPR entry for each scalar
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register that was saved in this batch. */
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for (int idx = 0; idx < count; idx++)
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{
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int stackaddr = offset + idx * 4;
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rtx dest = gen_rtx_MEM (SImode,
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gen_rtx_PLUS
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(DImode, sp,
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GEN_INT (stackaddr)));
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rtx src = gen_rtx_REG (SImode, saved_sgprs[start + idx]);
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rtx set = gen_rtx_SET (dest, src);
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RTX_FRAME_RELATED_P (set) = 1;
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RTVEC_ELT (seq, idx) = set;
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if (saved_sgprs[start + idx] == LINK_REGNUM)
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lrdest = stackaddr;
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}
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/* Add an additional expression for DWARF_LINK_REGISTER if
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LINK_REGNUM was saved. */
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if (lrdest != -1)
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{
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rtx dest = gen_rtx_MEM (DImode,
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gen_rtx_PLUS
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(DImode, sp,
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GEN_INT (lrdest)));
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rtx src = gen_rtx_REG (DImode, DWARF_LINK_REGISTER);
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rtx set = gen_rtx_SET (dest, src);
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RTX_FRAME_RELATED_P (set) = 1;
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RTVEC_ELT (seq, count) = set;
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}
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note = gen_rtx_SEQUENCE (VOIDmode, seq);
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}
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else
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{
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rtx dest = gen_rtx_MEM (V64SImode,
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gen_rtx_PLUS (DImode, sp,
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GEN_INT (offset)));
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rtx src = gen_rtx_REG (V64SImode, regno);
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note = gen_rtx_SET (dest, src);
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}
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RTX_FRAME_RELATED_P (insn) = 1;
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add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
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}
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else
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emit_insn (gen_gatherv64si_insn_1offset_exec
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(reg, vsp, const0_rtx, as, const0_rtx,
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@ -3224,8 +3287,7 @@ gcn_cannot_copy_insn_p (rtx_insn *insn)
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static enum unwind_info_type
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gcn_debug_unwind_info ()
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{
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/* No support for debug info, yet. */
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return UI_NONE;
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return UI_DWARF2;
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}
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/* Determine if there is a suitable hardware conversion instruction.
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@ -6251,6 +6313,8 @@ gcn_dwarf_register_number (unsigned int regno)
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return 768; */
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else if (regno == SCC_REG)
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return 128;
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else if (regno == DWARF_LINK_REGISTER)
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return 16;
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else if (SGPR_REGNO_P (regno))
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{
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if (regno - FIRST_SGPR_REG < 64)
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@ -6280,8 +6344,12 @@ gcn_dwarf_register_span (rtx rtl)
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if (GET_MODE_SIZE (mode) != 8)
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return NULL_RTX;
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rtx p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
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unsigned regno = REGNO (rtl);
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if (regno == DWARF_LINK_REGISTER)
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return NULL_RTX;
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rtx p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
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XVECEXP (p, 0, 0) = gen_rtx_REG (SImode, regno);
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XVECEXP (p, 0, 1) = gen_rtx_REG (SImode, regno + 1);
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@ -88,6 +88,7 @@
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#define FIRST_PARM_OFFSET(FNDECL) 0
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#define DYNAMIC_CHAIN_ADDRESS(FP) plus_constant (Pmode, (FP), -16)
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#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNUM)
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#define DWARF_FRAME_RETURN_COLUMN 16
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#define STACK_DYNAMIC_OFFSET(FNDECL) (-crtl->outgoing_args_size)
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#define ACCUMULATE_OUTGOING_ARGS 1
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#define RETURN_ADDR_RTX(COUNT,FRAMEADDR) \
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@ -138,7 +139,8 @@
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#define WORK_ITEM_ID_Z_REG 162
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#define SOFT_ARG_REG 416
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#define FRAME_POINTER_REGNUM 418
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#define FIRST_PSEUDO_REGISTER 420
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#define DWARF_LINK_REGISTER 420
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#define FIRST_PSEUDO_REGISTER 421
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#define FIRST_PARM_REG 24
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#define NUM_PARM_REGS 6
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@ -200,7 +202,7 @@
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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/* Other registers. */ \
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1, 1, 1, 1 \
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1, 1, 1, 1, 1 \
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}
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#define CALL_USED_REGISTERS { \
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@ -238,7 +240,7 @@
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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/* Other registers. */ \
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1, 1, 1, 1 \
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1, 1, 1, 1, 1 \
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}
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@ -517,7 +519,7 @@ enum gcn_address_spaces
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"v236", "v237", "v238", "v239", "v240", "v241", "v242", "v243", "v244", \
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"v245", "v246", "v247", "v248", "v249", "v250", "v251", "v252", "v253", \
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"v254", "v255", \
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"?ap0", "?ap1", "?fp0", "?fp1" }
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"?ap0", "?ap1", "?fp0", "?fp1", "?dwlr" }
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#define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE)
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#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
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