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PR tree-optimization/98335: New peephole2 xorl;movb -> movzbl

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This patch is the backend piece of my proposed fix to PR tree-opt/98335,
to allow C++ partial struct initialization to be as efficient/optimized
as full struct initialization.

With the middle-end patch just posted to gcc-patches, the test case
in the PR compiles on x86_64-pc-linux-gnu with -O2 to:

        xorl    %eax, %eax
        movb    c(%rip), %al
        ret

with this additional peephole2 (actually four peephole2s):

        movzbl  c(%rip), %eax
        ret

2022-03-11  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
	PR tree-optimization/98335
	* config/i386/i386.md (peephole2): Eliminate redundant insv.
	Combine movl followed by movb.  Transform xorl followed by
	a suitable movb or movw into the equivalent movz[bw]l.

gcc/testsuite/ChangeLog
	PR tree-optimization/98335
	* g++.target/i386/pr98335.C: New test case.
	* gcc.target/i386/pr98335.c: New test case.
This commit is contained in:
Roger Sayle 2022-03-11 17:57:12 +00:00
parent c5288df751
commit 251ea6dfbd
3 changed files with 80 additions and 0 deletions
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50
gcc/config/i386/i386.md
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@ -3180,6 +3180,38 @@
(const_int 8))
(subreg:SWI248 (match_dup 1) 0))])
;; Eliminate redundant insv, e.g. xorl %eax,%eax; movb $0, %ah
(define_peephole2
[(parallel [(set (match_operand:SWI48 0 "general_reg_operand")
(const_int 0))
(clobber (reg:CC FLAGS_REG))])
(set (zero_extract:SWI248 (match_operand:SWI248 1 "general_reg_operand")
(const_int 8)
(const_int 8))
(const_int 0))]
"REGNO (operands[0]) == REGNO (operands[1])"
[(parallel [(set (match_operand:SWI48 0 "general_reg_operand")
(const_int 0))
(clobber (reg:CC FLAGS_REG))])])
;; Combine movl followed by movb.
(define_peephole2
[(set (match_operand:SWI48 0 "general_reg_operand")
(match_operand:SWI48 1 "const_int_operand"))
(set (zero_extract:SWI248 (match_operand:SWI248 2 "general_reg_operand")
(const_int 8)
(const_int 8))
(match_operand:SWI248 3 "const_int_operand"))]
"REGNO (operands[0]) == REGNO (operands[2])"
[(set (match_operand:SWI48 0 "general_reg_operand")
(match_dup 4))]
{
HOST_WIDE_INT tmp = INTVAL (operands[1]) & ~(HOST_WIDE_INT)0xff00;
tmp |= (INTVAL (operands[3]) & 0xff) << 8;
operands[4] = gen_int_mode (tmp, <SWI48:MODE>mode);
})
(define_code_iterator any_extract [sign_extract zero_extract])
(define_insn "*insvqi_2"
@ -4276,6 +4308,24 @@
[(set_attr "isa" "*,avx512dq,avx512dq")
(set_attr "type" "imovx,mskmov,mskmov")
(set_attr "mode" "SI,QI,QI")])
;; Transform xorl; mov[bw] (set strict_low_part) into movz[bw]l.
(define_peephole2
[(parallel [(set (match_operand:SWI48 0 "general_reg_operand")
(const_int 0))
(clobber (reg:CC FLAGS_REG))])
(set (strict_low_part (match_operand:SWI12 1 "general_reg_operand"))
(match_operand:SWI12 2 "nonimmediate_operand"))]
"REGNO (operands[0]) == REGNO (operands[1])"
[(set (match_dup 0) (zero_extend:SWI48 (match_dup 2)))])
;; Likewise, but preserving FLAGS_REG.
(define_peephole2
[(set (match_operand:SWI48 0 "general_reg_operand") (const_int 0))
(set (strict_low_part (match_operand:SWI12 1 "general_reg_operand"))
(match_operand:SWI12 2 "nonimmediate_operand"))]
"REGNO (operands[0]) == REGNO (operands[1])"
[(set (match_dup 0) (zero_extend:SWI48 (match_dup 2)))])
;; Sign extension instructions

18
gcc/testsuite/g++.target/i386/pr98335.C Normal file
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@ -0,0 +1,18 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O2" } */
struct Data {
char a;
int b;
};
char c;
Data val(int idx) {
return { c }; // { dg-warning "extended initializer" "c++ 98" { target { c++98_only } } }
}
/* { dg-final { scan-assembler "movzbl" } } */
/* { dg-final { scan-assembler-not "xorl" } } */
/* { dg-final { scan-assembler-not "movb" } } */

12
gcc/testsuite/gcc.target/i386/pr98335.c Normal file
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@ -0,0 +1,12 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
union Data { char a; short b; };
char c;
void val(void) {
__asm__ __volatile__ ("" : : "r" ((union Data) { c } )); }
/* { dg-final { scan-assembler "movzbl" } } */
/* { dg-final { scan-assembler-not "xorl" } } */
/* { dg-final { scan-assembler-not "movb" } } */