[AArch64] Logical vector shift right conformance
gcc/ * config/aarch64/aarch64-simd-builtins.def (lshr): DI mode excluded. (lshr_simd): DI mode added. * config/aarch64/aarch64-simd.md (aarch64_lshr_simddi): New pattern. (aarch64_ushr_simddi): Likewise. * config/aarch64/aarch64.md (UNSPEC_USHR64): New unspec. * config/aarch64/arm_neon.h (vshr_n_u64): Intrinsic fixed. (vshrd_n_u64): Likewise. gcc/testsuite/ * gcc.target/aarch64/ushr64_1.c: New testcase. From-SVN: r208789
This commit is contained in:
Alex Velenko
James Greenhalgh
parent
71cfb0cfda
commit
252c7556e7
@ -1,3 +1,13 @@
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2014-03-24 Alex Velenko <Alex.Velenko@arm.com>
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* config/aarch64/aarch64-simd-builtins.def (lshr): DI mode excluded.
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(lshr_simd): DI mode added.
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* config/aarch64/aarch64-simd.md (aarch64_lshr_simddi): New pattern.
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(aarch64_ushr_simddi): Likewise.
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* config/aarch64/aarch64.md (UNSPEC_USHR64): New unspec.
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* config/aarch64/arm_neon.h (vshr_n_u64): Intrinsic fixed.
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(vshrd_n_u64): Likewise.
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2014-03-24 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
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* Makefile.in (s-macro_list): Depend on cc1.
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@ -183,6 +183,10 @@ aarch64_types_getlane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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#define TYPES_GETLANE (aarch64_types_getlane_qualifiers)
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#define TYPES_SHIFTIMM (aarch64_types_getlane_qualifiers)
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static enum aarch64_type_qualifiers
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aarch64_types_unsigned_shift_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_unsigned, qualifier_unsigned, qualifier_immediate };
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#define TYPES_USHIFTIMM (aarch64_types_unsigned_shift_qualifiers)
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static enum aarch64_type_qualifiers
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aarch64_types_setlane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate };
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#define TYPES_SETLANE (aarch64_types_setlane_qualifiers)
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@ -192,7 +192,8 @@
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BUILTIN_VDQ_I (SHIFTIMM, ashr, 3)
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VAR1 (SHIFTIMM, ashr_simd, 0, di)
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BUILTIN_VSDQ_I_DI (SHIFTIMM, lshr, 3)
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BUILTIN_VDQ_I (SHIFTIMM, lshr, 3)
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VAR1 (USHIFTIMM, lshr_simd, 0, di)
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/* Implemented by aarch64_<sur>shr_n<mode>. */
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BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0)
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BUILTIN_VSDQ_I_DI (SHIFTIMM, urshr_n, 0)
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@ -724,6 +724,31 @@
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DONE;
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})
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(define_expand "aarch64_lshr_simddi"
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[(match_operand:DI 0 "register_operand" "=w")
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(match_operand:DI 1 "register_operand" "w")
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(match_operand:SI 2 "aarch64_shift_imm64_di" "")]
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"TARGET_SIMD"
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{
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if (INTVAL (operands[2]) == 64)
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emit_insn (gen_aarch64_ushr_simddi (operands[0], operands[1]));
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else
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emit_insn (gen_lshrdi3 (operands[0], operands[1], operands[2]));
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DONE;
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}
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)
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;; SIMD shift by 64. This pattern is a special case as standard pattern does
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;; not handle NEON shifts by 64.
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(define_insn "aarch64_ushr_simddi"
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[(set (match_operand:DI 0 "register_operand" "=w")
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(unspec:DI
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[(match_operand:DI 1 "register_operand" "w")] UNSPEC_USHR64))]
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"TARGET_SIMD"
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"ushr\t%d0, %d1, 64"
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[(set_attr "type" "neon_shift_imm")]
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)
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(define_expand "vec_set<mode>"
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[(match_operand:VQ_S 0 "register_operand")
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(match_operand:<VEL> 1 "register_operand")
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@ -101,6 +101,7 @@
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UNSPEC_TLS
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UNSPEC_TLSDESC
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UNSPEC_USHL_2S
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UNSPEC_USHR64
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UNSPEC_VSTRUCTDUMMY
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])
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@ -23364,7 +23364,7 @@ vshr_n_u32 (uint32x2_t __a, const int __b)
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__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
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vshr_n_u64 (uint64x1_t __a, const int __b)
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{
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return (uint64x1_t) __builtin_aarch64_lshrdi ((int64x1_t) __a, __b);
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return __builtin_aarch64_lshr_simddi_uus ( __a, __b);
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}
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__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
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@ -23421,10 +23421,10 @@ vshrd_n_s64 (int64x1_t __a, const int __b)
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return (int64x1_t) __builtin_aarch64_ashr_simddi (__a, __b);
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}
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__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
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vshrd_n_u64 (uint64x1_t __a, const int __b)
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__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
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vshrd_n_u64 (uint64_t __a, const int __b)
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{
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return (uint64x1_t) __builtin_aarch64_lshrdi (__a, __b);
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return __builtin_aarch64_lshr_simddi_uus (__a, __b);
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}
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/* vsli */
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@ -1,3 +1,7 @@
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2014-03-24 Alex Velenko <Alex.Velenko@arm.com>
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* gcc.target/aarch64/ushr64_1.c: New.
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2014-03-24 James Greenhalgh <james.greenhalgh@arm.com>
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* gcc.target/aarch64/vect-abs.c (dg-options): Add -std=c99.
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84
gcc/testsuite/gcc.target/aarch64/ushr64_1.c
Normal file
84
gcc/testsuite/gcc.target/aarch64/ushr64_1.c
Normal file
@ -0,0 +1,84 @@
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/* Test logical SIMD shift works correctly. */
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/* { dg-do run } */
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/* { dg-options "--save-temps" } */
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#include "arm_neon.h"
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extern void abort (void);
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int __attribute__ ((noinline))
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test_vshr_n_u64_64 (uint64x1_t passed, uint64_t expected)
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{
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return vget_lane_u64 (vshr_n_u64 (passed, 64), 0) != expected;
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}
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int __attribute__ ((noinline))
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test_vshr_n_u64_4 (uint64x1_t passed, uint64_t expected)
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{
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return vget_lane_u64 (vshr_n_u64 (passed, 4), 0) != expected;
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}
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int __attribute__ ((noinline))
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test_vshr_n_u64_0 (uint64x1_t passed, uint64_t expected)
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{
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return vget_lane_u64 (vshr_n_u64 (passed, 0), 0) != expected;
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}
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int __attribute__ ((noinline))
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test_vshrd_n_u64_64 (uint64_t passed, uint64_t expected)
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{
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return vshrd_n_u64 (passed, 64) != expected;
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}
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int __attribute__ ((noinline))
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test_vshrd_n_u64_4 (uint64_t passed, uint64_t expected)
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{
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return vshrd_n_u64 (passed, 4) != expected;
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}
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int __attribute__ ((noinline))
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test_vshrd_n_u64_0 (uint64_t passed, uint64_t expected)
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{
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return vshrd_n_u64 (passed, 0) != expected;
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}
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/* { dg-final { scan-assembler-times "ushr\\td\[0-9\]+, d\[0-9\]+, 64" 2 } } */
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/* { dg-final { (scan-assembler-times "ushr\\td\[0-9\]+, d\[0-9\]+, 4" 2) || \
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(scan-assembler-times "lsr\\tx\[0-9\]+, x\[0-9\]+, 4" 2) } } */
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/* { dg-final { scan-assembler-not "ushr\\td\[0-9\]+, d\[0-9\]+, 0" } } */
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int
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main (int argc, char *argv[])
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{
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/* Testing vshr_n_u64. */
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if (test_vshr_n_u64_64 (vcreate_u64 (0x0000000080000000), 0))
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abort ();
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if (test_vshr_n_u64_64 (vcreate_u64 (0xffffffff80000000), 0))
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abort ();
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if (test_vshr_n_u64_4 (vcreate_u64 (0x0000000080000000), 0x0000000008000000))
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abort ();
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if (test_vshr_n_u64_4 (vcreate_u64 (0xffffffff80000000), 0x0ffffffff8000000))
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abort ();
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if (test_vshr_n_u64_0 (vcreate_u64 (0x0000000080000000), 0x0000000080000000))
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abort ();
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/* Testing vshrd_n_u64. */
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if (test_vshrd_n_u64_64 (0x0000000080000000, 0))
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abort ();
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if (test_vshrd_n_u64_64 (0xffffffff80000000, 0))
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abort ();
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if (test_vshrd_n_u64_4 (0x0000000080000000, 0x0000000008000000))
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abort ();
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if (test_vshrd_n_u64_4 (0xffffffff80000000, 0x0ffffffff8000000))
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abort ();
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if (test_vshrd_n_u64_0 (0x0000000080000000, 0x0000000080000000))
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abort ();
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return 0;
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}
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/* { dg-final { cleanup-saved-temps } } */
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