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rs6000.c (RELOAD_REG_AND_M16): Add support for Altivec style vector loads that ignore the bottom 3 bits of the...

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[gcc]
2014-11-17  Michael Meissner  <meissner@linux.vnet.ibm.com>
	    Ulrich Weigand  <Ulrich.Weigand@de.ibm.com>

	* config/rs6000/rs6000.c (RELOAD_REG_AND_M16): Add support for
	Altivec style vector loads that ignore the bottom 3 bits of the
	address.
	(rs6000_debug_addr_mask): New function to print the addr_mask
	values if debugging.
	(rs6000_debug_print_mode): Call rs6000_debug_addr_mask to print
	out addr_mask.
	(rs6000_setup_reg_addr_masks): Add support for Altivec style
	vector loads that ignore the bottom 3 bits of the address.  Allow
	pre-increment and pre-decrement on floating point, even if the
	-mupper-regs-{sf,df} options were used.
	(rs6000_init_hard_regno_mode_ok): Rework DFmode support if
	-mupper-regs-df.  Add support for -mupper-regs-sf.  Rearrange code
	placement for direct move support.
	(rs6000_option_override_internal): Add checks for -mupper-regs-df
	requiring -mvsx, and -mupper-regs-sf requiring -mpower8-vector.
	If -mupper-regs, set both -mupper-regs-sf and -mupper-regs-df,
	depending on the underlying cpu.
	(rs6000_secondary_reload_fail): Add ATTRIBUTE_NORETURN.
	(rs6000_secondary_reload_toc_costs): Helper function to identify
	costs of a TOC load for secondary reload support.
	(rs6000_secondary_reload_memory): Helper function for secondary
	reload, to determine if a particular memory operation is directly
	handled by the hardware, or if it needs support from secondary
	reload to create a valid address.
	(rs6000_secondary_reload): Rework code, to be clearer.  If the
	appropriate -mupper-regs-{sf,df} is used, use FPR registers to
	reload scalar values, since the FPR registers have D-form
	addressing. Move most of the code handling memory to the function
	rs6000_secondary_reload_memory, and use the reg_addr structure to
	determine what type of address modes are supported.  Print more
	debug information if -mdebug=addr.
	(rs6000_secondary_reload_inner): Rework entire function to be more
	general.  Use the reg_addr bits to determine what type of
	addressing is supported.
	(rs6000_preferred_reload_class): Rework.  Move constant handling
	into a single place.  Prefer using FLOAT_REGS for scalar floating
	point.
	(rs6000_secondary_reload_class): Use a FPR register to move a
	value from an Altivec register to a GPR, and vice versa.  Move VSX
	handling above traditional floating point.

	* config/rs6000/rs6000.md (mov<mode>_hardfloat, FMOVE32 case):
	Delete some spaces in the constraints.
	(DF->DF move peephole2): Disable if -mupper-regs-{sf,df} to
	allow using FPR registers to load/store an Altivec register for
	scalar floating point types.
	(SF->SF move peephole2): Likewise.
	(DFmode splitter): Add a define_split to move floating point
	constants to the constant pool before register allocation.
	Normally constants are put into the pool immediately, but
	-ffast-math delays putting them into the constant pool for the
	reciprocal approximation support.
	(SFmode splitter): Likewise.

	* config/rs6000/rs6000.opt (-mupper-regs-df): Make option public.
	(-mupper-regs-sf): Likewise.

	* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
	__UPPER_REGS_DF__ if -mupper-regs-df.  Define __UPPER_REGS_SF__ if
	-mupper-regs-sf.
	(-mupper-regs): New combination option that sets -mupper-regs-sf
	and -mupper-regs-df by default if the cpu supports the instructions.

	* doc/invoke.texi (RS/6000 and PowerPC Options): Document
	-mupper-regs, -mupper-regs-sf, and -mupper-regs-df.

	* config/rs6000/predicates.md (memory_fp_constant): New predicate
	to return true if the operand is a floating point constant that
	must be put into the constant pool, before register allocation
	occurs.

	* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Enable
	-mupper-regs-df by default.
	(ISA_2_7_MASKS_SERVER): Enable -mupper-regs-sf by default.
	(POWERPC_MASKS): Add -mupper-regs-{sf,df} as options set by the
	various -mcpu=... options.
	(power7 cpu): Enable -mupper-regs-df by default.

	* doc/invoke.texi (RS/6000 and PowerPC Options): Document
	-mupper-regs.

[gcc/testsuite]
2014-11-17  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/p8vector-ldst.c: Rewrite to use 40 live
	floating point variables instead of using asm to test allocating
	values to the Altivec registers.

	* gcc.target/powerpc/upper-regs-sf.c: New -mupper-regs-sf and
	-mupper-regs-df tests.
	* gcc.target/powerpc/upper-regs-df.c: Likewise.

	* config/rs6000/predicates.md (memory_fp_constant): New predicate


Co-Authored-By: Ulrich Weigand <uweigand@de.ibm.com>

From-SVN: r217679
This commit is contained in:
Michael Meissner 2014-11-17 22:32:26 +00:00 committed by Michael Meissner
parent 5a4e7cade9
commit 25adc5d044
12 changed files with 2969 additions and 496 deletions
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85
gcc/ChangeLog
View File

@ -1,3 +1,88 @@
2014-11-17 Michael Meissner <meissner@linux.vnet.ibm.com>
Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
* config/rs6000/rs6000.c (RELOAD_REG_AND_M16): Add support for
Altivec style vector loads that ignore the bottom 3 bits of the
address.
(rs6000_debug_addr_mask): New function to print the addr_mask
values if debugging.
(rs6000_debug_print_mode): Call rs6000_debug_addr_mask to print
out addr_mask.
(rs6000_setup_reg_addr_masks): Add support for Altivec style
vector loads that ignore the bottom 3 bits of the address. Allow
pre-increment and pre-decrement on floating point, even if the
-mupper-regs-{sf,df} options were used.
(rs6000_init_hard_regno_mode_ok): Rework DFmode support if
-mupper-regs-df. Add support for -mupper-regs-sf. Rearrange code
placement for direct move support.
(rs6000_option_override_internal): Add checks for -mupper-regs-df
requiring -mvsx, and -mupper-regs-sf requiring -mpower8-vector.
If -mupper-regs, set both -mupper-regs-sf and -mupper-regs-df,
depending on the underlying cpu.
(rs6000_secondary_reload_fail): Add ATTRIBUTE_NORETURN.
(rs6000_secondary_reload_toc_costs): Helper function to identify
costs of a TOC load for secondary reload support.
(rs6000_secondary_reload_memory): Helper function for secondary
reload, to determine if a particular memory operation is directly
handled by the hardware, or if it needs support from secondary
reload to create a valid address.
(rs6000_secondary_reload): Rework code, to be clearer. If the
appropriate -mupper-regs-{sf,df} is used, use FPR registers to
reload scalar values, since the FPR registers have D-form
addressing. Move most of the code handling memory to the function
rs6000_secondary_reload_memory, and use the reg_addr structure to
determine what type of address modes are supported. Print more
debug information if -mdebug=addr.
(rs6000_secondary_reload_inner): Rework entire function to be more
general. Use the reg_addr bits to determine what type of
addressing is supported.
(rs6000_preferred_reload_class): Rework. Move constant handling
into a single place. Prefer using FLOAT_REGS for scalar floating
point.
(rs6000_secondary_reload_class): Use a FPR register to move a
value from an Altivec register to a GPR, and vice versa. Move VSX
handling above traditional floating point.
* config/rs6000/rs6000.md (mov<mode>_hardfloat, FMOVE32 case):
Delete some spaces in the constraints.
(DF->DF move peephole2): Disable if -mupper-regs-{sf,df} to
allow using FPR registers to load/store an Altivec register for
scalar floating point types.
(SF->SF move peephole2): Likewise.
(DFmode splitter): Add a define_split to move floating point
constants to the constant pool before register allocation.
Normally constants are put into the pool immediately, but
-ffast-math delays putting them into the constant pool for the
reciprocal approximation support.
(SFmode splitter): Likewise.
* config/rs6000/rs6000.opt (-mupper-regs-df): Make option public.
(-mupper-regs-sf): Likewise.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
__UPPER_REGS_DF__ if -mupper-regs-df. Define __UPPER_REGS_SF__ if
-mupper-regs-sf.
(-mupper-regs): New combination option that sets -mupper-regs-sf
and -mupper-regs-df by default if the cpu supports the instructions.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mupper-regs, -mupper-regs-sf, and -mupper-regs-df.
* config/rs6000/predicates.md (memory_fp_constant): New predicate
to return true if the operand is a floating point constant that
must be put into the constant pool, before register allocation
occurs.
* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Enable
-mupper-regs-df by default.
(ISA_2_7_MASKS_SERVER): Enable -mupper-regs-sf by default.
(POWERPC_MASKS): Add -mupper-regs-{sf,df} as options set by the
various -mcpu=... options.
(power7 cpu): Enable -mupper-regs-df by default.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mupper-regs.
2014-11-17 Zhouyi Zhou <yizhouzhou@ict.ac.cn>
* ira-conflicts.c (build_conflict_bit_table): Add the current

21
gcc/config/rs6000/predicates.md
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@ -521,6 +521,27 @@
}
})
;; Return 1 if the operand must be loaded from memory. This is used by a
;; define_split to insure constants get pushed to the constant pool before
;; reload. If -ffast-math is used, easy_fp_constant will allow move insns to
;; have constants in order not interfere with reciprocal estimation. However,
;; with -mupper-regs support, these constants must be moved to the constant
;; pool before register allocation.
(define_predicate "memory_fp_constant"
(match_code "const_double")
{
if (TARGET_VSX && op == CONST0_RTX (mode))
return 0;
if (!TARGET_HARD_FLOAT || !TARGET_FPRS
|| (mode == SFmode && !TARGET_SINGLE_FLOAT)
|| (mode == DFmode && !TARGET_DOUBLE_FLOAT))
return 0;
return 1;
})
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"

4
gcc/config/rs6000/rs6000-c.c
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@ -380,6 +380,10 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__");
if ((flags & OPTION_MASK_CRYPTO) != 0)
rs6000_define_or_undefine_macro (define_p, "__CRYPTO__");
if ((flags & OPTION_MASK_UPPER_REGS_DF) != 0)
rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_DF__");
if ((flags & OPTION_MASK_UPPER_REGS_SF) != 0)
rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_SF__");
/* options from the builtin masks. */
if ((bu_mask & RS6000_BTM_SPE) != 0)

10
gcc/config/rs6000/rs6000-cpus.def
View File

@ -44,7 +44,8 @@
#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
| OPTION_MASK_POPCNTD \
| OPTION_MASK_ALTIVEC \
| OPTION_MASK_VSX)
| OPTION_MASK_VSX \
| OPTION_MASK_UPPER_REGS_DF)
/* For now, don't provide an embedded version of ISA 2.07. */
#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
@ -54,7 +55,8 @@
| OPTION_MASK_DIRECT_MOVE \
| OPTION_MASK_HTM \
| OPTION_MASK_QUAD_MEMORY \
| OPTION_MASK_QUAD_MEMORY_ATOMIC)
| OPTION_MASK_QUAD_MEMORY_ATOMIC \
| OPTION_MASK_UPPER_REGS_SF)
#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
@ -94,6 +96,8 @@
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
| OPTION_MASK_UPPER_REGS_DF \
| OPTION_MASK_UPPER_REGS_SF \
| OPTION_MASK_VSX \
| OPTION_MASK_VSX_TIMODE)
@ -184,7 +188,7 @@ RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
RS6000_CPU ("power7", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */
POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
| MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
| MASK_VSX | MASK_RECIP_PRECISION)
| MASK_VSX | MASK_RECIP_PRECISION | OPTION_MASK_UPPER_REGS_DF)
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)

1180
gcc/config/rs6000/rs6000.c
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File diff suppressed because it is too large Load Diff

23
gcc/config/rs6000/rs6000.md
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@ -7850,7 +7850,7 @@
(define_insn "mov<mode>_hardfloat"
[(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,<f32_vsx>,<f32_vsx>,<f32_lr>,<f32_sm>,<f32_av>,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
(match_operand:FMOVE32 1 "input_operand" "r,m,r,f,<f32_vsx>,j,<f32_lm>,<f32_sr>,Z,<f32_av>,r,<f32_dm>,r, h, 0, G,Fn"))]
(match_operand:FMOVE32 1 "input_operand" "r,m,r,f,<f32_vsx>,j,<f32_lm>,<f32_sr>,Z,<f32_av>,r,<f32_dm>,r,h,0,G,Fn"))]
"(gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))
&& (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
@ -8137,6 +8137,21 @@
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
[(set_attr "length" "20,20,16")])
;; If we are using -ffast-math, easy_fp_constant assumes all constants are
;; 'easy' in order to allow for reciprocal estimation. Make sure the constant
;; is in the constant pool before reload occurs. This simplifies accessing
;; scalars in the traditional Altivec registers.
(define_split
[(set (match_operand:SFDF 0 "register_operand" "")
(match_operand:SFDF 1 "memory_fp_constant" ""))]
"TARGET_<MODE>_FPR && flag_unsafe_math_optimizations
&& !reload_in_progress && !reload_completed && !lra_in_progress"
[(set (match_dup 0) (match_dup 2))]
{
operands[2] = validize_mem (force_const_mem (<MODE>mode, operands[1]));
})
(define_expand "extenddftf2"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(float_extend:TF (match_operand:DF 1 "input_operand" "")))]
@ -9816,12 +9831,15 @@
;; sequences, using get_attr_length here will smash the operands
;; array. Neither is there an early_cobbler_p predicate.
;; Disallow subregs for E500 so we don't munge frob_di_df_2.
;; Also this optimization interferes with scalars going into
;; altivec registers (the code does reloading through the FPRs).
(define_peephole2
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(match_operand:DF 1 "any_operand" ""))
(set (match_operand:DF 2 "gpc_reg_operand" "")
(match_dup 0))]
"!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
&& !TARGET_UPPER_REGS_DF
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (match_dup 1))])
@ -9830,7 +9848,8 @@
(match_operand:SF 1 "any_operand" ""))
(set (match_operand:SF 2 "gpc_reg_operand" "")
(match_dup 0))]
"peep2_reg_dead_p (2, operands[0])"
"!TARGET_UPPER_REGS_SF
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (match_dup 1))])

10
gcc/config/rs6000/rs6000.opt
View File

@ -582,12 +582,16 @@ Target Report Var(rs6000_compat_align_parm) Init(0) Save
Generate aggregate parameter passing code with at most 64-bit alignment.
mupper-regs-df
Target Undocumented Mask(UPPER_REGS_DF) Var(rs6000_isa_flags)
Target Report Mask(UPPER_REGS_DF) Var(rs6000_isa_flags)
Allow double variables in upper registers with -mcpu=power7 or -mvsx
mupper-regs-sf
Target Undocumented Mask(UPPER_REGS_SF) Var(rs6000_isa_flags)
Allow float variables in upper registers with -mcpu=power8 or -mp8-vector
Target Report Mask(UPPER_REGS_SF) Var(rs6000_isa_flags)
Allow float variables in upper registers with -mcpu=power8 or -mpower8-vector
mupper-regs
Target Report Var(TARGET_UPPER_REGS) Init(-1) Save
Allow float/double variables in upper registers if cpu allows it
moptimize-swaps
Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save

37
gcc/doc/invoke.texi
View File

@ -940,7 +940,9 @@ See RS/6000 and PowerPC Options.
-mcrypto -mno-crypto -mdirect-move -mno-direct-move @gol
-mquad-memory -mno-quad-memory @gol
-mquad-memory-atomic -mno-quad-memory-atomic @gol
-mcompat-align-parm -mno-compat-align-parm}
-mcompat-align-parm -mno-compat-align-parm @gol
-mupper-regs-df -mno-upper-regs-df -mupper-regs-sf -mno-upper-regs-sf @gol
-mupper-regs -mno-upper-regs}
@emph{RX Options}
@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol
@ -19729,6 +19731,39 @@ Generate code that uses (does not use) the atomic quad word memory
instructions. The @option{-mquad-memory-atomic} option requires use of
64-bit mode.
@item -mupper-regs-df
@itemx -mno-upper-regs-df
@opindex mupper-regs-df
@opindex mno-upper-regs-df
Generate code that uses (does not use) the scalar double precision
instructions that target all 64 registers in the vector/scalar
floating point register set that were added in version 2.06 of the
PowerPC ISA. The @option{-mupper-regs-df} turned on by default if you
use either of the @option{-mcpu=power7}, @option{-mcpu=power8}, or
@option{-mvsx} options.
@item -mupper-regs-sf
@itemx -mno-upper-regs-sf
@opindex mupper-regs-sf
@opindex mno-upper-regs-sf
Generate code that uses (does not use) the scalar single precision
instructions that target all 64 registers in the vector/scalar
floating point register set that were added in version 2.07 of the
PowerPC ISA. The @option{-mupper-regs-sf} turned on by default if you
use either of the @option{-mcpu=power8}, or @option{-mpower8-vector}
options.
@item -mupper-regs
@itemx -mno-upper-regs
@opindex mupper-regs
@opindex mno-upper-regs
Generate code that uses (does not use) the scalar
instructions that target all 64 registers in the vector/scalar
floating point register set, depending on the model of the machine.
If the @option{-mno-upper-regs} option was used, it will turn off both
@option{-mupper-regs-sf} and @option{-mupper-regs-df} options.
@item -mfloat-gprs=@var{yes/single/double/no}
@itemx -mfloat-gprs
@opindex mfloat-gprs

12
gcc/testsuite/ChangeLog
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@ -1,3 +1,15 @@
2014-11-17 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p8vector-ldst.c: Rewrite to use 40 live
floating point variables instead of using asm to test allocating
values to the Altivec registers.
* gcc.target/powerpc/upper-regs-sf.c: New -mupper-regs-sf and
-mupper-regs-df tests.
* gcc.target/powerpc/upper-regs-df.c: Likewise.
* config/rs6000/predicates.md (memory_fp_constant): New predicate
2014-11-17 Tom de Vries <tom@codesourcery.com>
* gcc.dg/pr43864-2.c: Add -ftree-tail-merge to dg-options.

631
gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c
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@ -1,43 +1,624 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */
float load_sf (float *p)
float
load_store_sf (unsigned long num,
const float *from_ptr,
float *to_ptr,
const unsigned long *in_mask_ptr,
const unsigned long *out_mask_ptr)
{
float f = *p;
__asm__ ("# reg %x0" : "+v" (f));
return f;
float value00 = 0.0f;
float value01 = 0.0f;
float value02 = 0.0f;
float value03 = 0.0f;
float value04 = 0.0f;
float value05 = 0.0f;
float value06 = 0.0f;
float value07 = 0.0f;
float value08 = 0.0f;
float value09 = 0.0f;
float value10 = 0.0f;
float value11 = 0.0f;
float value12 = 0.0f;
float value13 = 0.0f;
float value14 = 0.0f;
float value15 = 0.0f;
float value16 = 0.0f;
float value17 = 0.0f;
float value18 = 0.0f;
float value19 = 0.0f;
float value20 = 0.0f;
float value21 = 0.0f;
float value22 = 0.0f;
float value23 = 0.0f;
float value24 = 0.0f;
float value25 = 0.0f;
float value26 = 0.0f;
float value27 = 0.0f;
float value28 = 0.0f;
float value29 = 0.0f;
float value30 = 0.0f;
float value31 = 0.0f;
float value32 = 0.0f;
float value33 = 0.0f;
float value34 = 0.0f;
float value35 = 0.0f;
float value36 = 0.0f;
float value37 = 0.0f;
float value38 = 0.0f;
float value39 = 0.0f;
unsigned long in_mask;
unsigned long out_mask;
unsigned long i;
for (i = 0; i < num; i++)
{
in_mask = *in_mask_ptr++;
if ((in_mask & (1L << 0)) != 0L)
value00 = *from_ptr++;
if ((in_mask & (1L << 1)) != 0L)
value01 = *from_ptr++;
if ((in_mask & (1L << 2)) != 0L)
value02 = *from_ptr++;
if ((in_mask & (1L << 3)) != 0L)
value03 = *from_ptr++;
if ((in_mask & (1L << 4)) != 0L)
value04 = *from_ptr++;
if ((in_mask & (1L << 5)) != 0L)
value05 = *from_ptr++;
if ((in_mask & (1L << 6)) != 0L)
value06 = *from_ptr++;
if ((in_mask & (1L << 7)) != 0L)
value07 = *from_ptr++;
if ((in_mask & (1L << 8)) != 0L)
value08 = *from_ptr++;
if ((in_mask & (1L << 9)) != 0L)
value09 = *from_ptr++;
if ((in_mask & (1L << 10)) != 0L)
value10 = *from_ptr++;
if ((in_mask & (1L << 11)) != 0L)
value11 = *from_ptr++;
if ((in_mask & (1L << 12)) != 0L)
value12 = *from_ptr++;
if ((in_mask & (1L << 13)) != 0L)
value13 = *from_ptr++;
if ((in_mask & (1L << 14)) != 0L)
value14 = *from_ptr++;
if ((in_mask & (1L << 15)) != 0L)
value15 = *from_ptr++;
if ((in_mask & (1L << 16)) != 0L)
value16 = *from_ptr++;
if ((in_mask & (1L << 17)) != 0L)
value17 = *from_ptr++;
if ((in_mask & (1L << 18)) != 0L)
value18 = *from_ptr++;
if ((in_mask & (1L << 19)) != 0L)
value19 = *from_ptr++;
if ((in_mask & (1L << 20)) != 0L)
value20 = *from_ptr++;
if ((in_mask & (1L << 21)) != 0L)
value21 = *from_ptr++;
if ((in_mask & (1L << 22)) != 0L)
value22 = *from_ptr++;
if ((in_mask & (1L << 23)) != 0L)
value23 = *from_ptr++;
if ((in_mask & (1L << 24)) != 0L)
value24 = *from_ptr++;
if ((in_mask & (1L << 25)) != 0L)
value25 = *from_ptr++;
if ((in_mask & (1L << 26)) != 0L)
value26 = *from_ptr++;
if ((in_mask & (1L << 27)) != 0L)
value27 = *from_ptr++;
if ((in_mask & (1L << 28)) != 0L)
value28 = *from_ptr++;
if ((in_mask & (1L << 29)) != 0L)
value29 = *from_ptr++;
if ((in_mask & (1L << 30)) != 0L)
value30 = *from_ptr++;
if ((in_mask & (1L << 31)) != 0L)
value31 = *from_ptr++;
if ((in_mask & (1L << 32)) != 0L)
value32 = *from_ptr++;
if ((in_mask & (1L << 33)) != 0L)
value33 = *from_ptr++;
if ((in_mask & (1L << 34)) != 0L)
value34 = *from_ptr++;
if ((in_mask & (1L << 35)) != 0L)
value35 = *from_ptr++;
if ((in_mask & (1L << 36)) != 0L)
value36 = *from_ptr++;
if ((in_mask & (1L << 37)) != 0L)
value37 = *from_ptr++;
if ((in_mask & (1L << 38)) != 0L)
value38 = *from_ptr++;
if ((in_mask & (1L << 39)) != 0L)
value39 = *from_ptr++;
out_mask = *out_mask_ptr++;
if ((out_mask & (1L << 0)) != 0L)
*to_ptr++ = value00;
if ((out_mask & (1L << 1)) != 0L)
*to_ptr++ = value01;
if ((out_mask & (1L << 2)) != 0L)
*to_ptr++ = value02;
if ((out_mask & (1L << 3)) != 0L)
*to_ptr++ = value03;
if ((out_mask & (1L << 4)) != 0L)
*to_ptr++ = value04;
if ((out_mask & (1L << 5)) != 0L)
*to_ptr++ = value05;
if ((out_mask & (1L << 6)) != 0L)
*to_ptr++ = value06;
if ((out_mask & (1L << 7)) != 0L)
*to_ptr++ = value07;
if ((out_mask & (1L << 8)) != 0L)
*to_ptr++ = value08;
if ((out_mask & (1L << 9)) != 0L)
*to_ptr++ = value09;
if ((out_mask & (1L << 10)) != 0L)
*to_ptr++ = value10;
if ((out_mask & (1L << 11)) != 0L)
*to_ptr++ = value11;
if ((out_mask & (1L << 12)) != 0L)
*to_ptr++ = value12;
if ((out_mask & (1L << 13)) != 0L)
*to_ptr++ = value13;
if ((out_mask & (1L << 14)) != 0L)
*to_ptr++ = value14;
if ((out_mask & (1L << 15)) != 0L)
*to_ptr++ = value15;
if ((out_mask & (1L << 16)) != 0L)
*to_ptr++ = value16;
if ((out_mask & (1L << 17)) != 0L)
*to_ptr++ = value17;
if ((out_mask & (1L << 18)) != 0L)
*to_ptr++ = value18;
if ((out_mask & (1L << 19)) != 0L)
*to_ptr++ = value19;
if ((out_mask & (1L << 20)) != 0L)
*to_ptr++ = value20;
if ((out_mask & (1L << 21)) != 0L)
*to_ptr++ = value21;
if ((out_mask & (1L << 22)) != 0L)
*to_ptr++ = value22;
if ((out_mask & (1L << 23)) != 0L)
*to_ptr++ = value23;
if ((out_mask & (1L << 24)) != 0L)
*to_ptr++ = value24;
if ((out_mask & (1L << 25)) != 0L)
*to_ptr++ = value25;
if ((out_mask & (1L << 26)) != 0L)
*to_ptr++ = value26;
if ((out_mask & (1L << 27)) != 0L)
*to_ptr++ = value27;
if ((out_mask & (1L << 28)) != 0L)
*to_ptr++ = value28;
if ((out_mask & (1L << 29)) != 0L)
*to_ptr++ = value29;
if ((out_mask & (1L << 30)) != 0L)
*to_ptr++ = value30;
if ((out_mask & (1L << 31)) != 0L)
*to_ptr++ = value31;
if ((out_mask & (1L << 32)) != 0L)
*to_ptr++ = value32;
if ((out_mask & (1L << 33)) != 0L)
*to_ptr++ = value33;
if ((out_mask & (1L << 34)) != 0L)
*to_ptr++ = value34;
if ((out_mask & (1L << 35)) != 0L)
*to_ptr++ = value35;
if ((out_mask & (1L << 36)) != 0L)
*to_ptr++ = value36;
if ((out_mask & (1L << 37)) != 0L)
*to_ptr++ = value37;
if ((out_mask & (1L << 38)) != 0L)
*to_ptr++ = value38;
if ((out_mask & (1L << 39)) != 0L)
*to_ptr++ = value39;
}
return ( value00 + value01 + value02 + value03 + value04
+ value05 + value06 + value07 + value08 + value09
+ value10 + value11 + value12 + value13 + value14
+ value15 + value16 + value17 + value18 + value19
+ value20 + value21 + value22 + value23 + value24
+ value25 + value26 + value27 + value28 + value29
+ value30 + value31 + value32 + value33 + value34
+ value35 + value36 + value37 + value38 + value39);
}
double load_df (double *p)
double
load_store_df (unsigned long num,
const double *from_ptr,
double *to_ptr,
const unsigned long *in_mask_ptr,
const unsigned long *out_mask_ptr)
{
double d = *p;
__asm__ ("# reg %x0" : "+v" (d));
return d;
}
double value00 = 0.0;
double value01 = 0.0;
double value02 = 0.0;
double value03 = 0.0;
double value04 = 0.0;
double value05 = 0.0;
double value06 = 0.0;
double value07 = 0.0;
double value08 = 0.0;
double value09 = 0.0;
double value10 = 0.0;
double value11 = 0.0;
double value12 = 0.0;
double value13 = 0.0;
double value14 = 0.0;
double value15 = 0.0;
double value16 = 0.0;
double value17 = 0.0;
double value18 = 0.0;
double value19 = 0.0;
double value20 = 0.0;
double value21 = 0.0;
double value22 = 0.0;
double value23 = 0.0;
double value24 = 0.0;
double value25 = 0.0;
double value26 = 0.0;
double value27 = 0.0;
double value28 = 0.0;
double value29 = 0.0;
double value30 = 0.0;
double value31 = 0.0;
double value32 = 0.0;
double value33 = 0.0;
double value34 = 0.0;
double value35 = 0.0;
double value36 = 0.0;
double value37 = 0.0;
double value38 = 0.0;
double value39 = 0.0;
unsigned long in_mask;
unsigned long out_mask;
unsigned long i;
double load_dfsf (float *p)
{
double d = (double) *p;
__asm__ ("# reg %x0" : "+v" (d));
return d;
}
for (i = 0; i < num; i++)
{
in_mask = *in_mask_ptr++;
if ((in_mask & (1L << 0)) != 0L)
value00 = *from_ptr++;
void store_sf (float *p, float f)
{
__asm__ ("# reg %x0" : "+v" (f));
*p = f;
}
if ((in_mask & (1L << 1)) != 0L)
value01 = *from_ptr++;
void store_df (double *p, double d)
{
__asm__ ("# reg %x0" : "+v" (d));
*p = d;
if ((in_mask & (1L << 2)) != 0L)
value02 = *from_ptr++;
if ((in_mask & (1L << 3)) != 0L)
value03 = *from_ptr++;
if ((in_mask & (1L << 4)) != 0L)
value04 = *from_ptr++;
if ((in_mask & (1L << 5)) != 0L)
value05 = *from_ptr++;
if ((in_mask & (1L << 6)) != 0L)
value06 = *from_ptr++;
if ((in_mask & (1L << 7)) != 0L)
value07 = *from_ptr++;
if ((in_mask & (1L << 8)) != 0L)
value08 = *from_ptr++;
if ((in_mask & (1L << 9)) != 0L)
value09 = *from_ptr++;
if ((in_mask & (1L << 10)) != 0L)
value10 = *from_ptr++;
if ((in_mask & (1L << 11)) != 0L)
value11 = *from_ptr++;
if ((in_mask & (1L << 12)) != 0L)
value12 = *from_ptr++;
if ((in_mask & (1L << 13)) != 0L)
value13 = *from_ptr++;
if ((in_mask & (1L << 14)) != 0L)
value14 = *from_ptr++;
if ((in_mask & (1L << 15)) != 0L)
value15 = *from_ptr++;
if ((in_mask & (1L << 16)) != 0L)
value16 = *from_ptr++;
if ((in_mask & (1L << 17)) != 0L)
value17 = *from_ptr++;
if ((in_mask & (1L << 18)) != 0L)
value18 = *from_ptr++;
if ((in_mask & (1L << 19)) != 0L)
value19 = *from_ptr++;
if ((in_mask & (1L << 20)) != 0L)
value20 = *from_ptr++;
if ((in_mask & (1L << 21)) != 0L)
value21 = *from_ptr++;
if ((in_mask & (1L << 22)) != 0L)
value22 = *from_ptr++;
if ((in_mask & (1L << 23)) != 0L)
value23 = *from_ptr++;
if ((in_mask & (1L << 24)) != 0L)
value24 = *from_ptr++;
if ((in_mask & (1L << 25)) != 0L)
value25 = *from_ptr++;
if ((in_mask & (1L << 26)) != 0L)
value26 = *from_ptr++;
if ((in_mask & (1L << 27)) != 0L)
value27 = *from_ptr++;
if ((in_mask & (1L << 28)) != 0L)
value28 = *from_ptr++;
if ((in_mask & (1L << 29)) != 0L)
value29 = *from_ptr++;
if ((in_mask & (1L << 30)) != 0L)
value30 = *from_ptr++;
if ((in_mask & (1L << 31)) != 0L)
value31 = *from_ptr++;
if ((in_mask & (1L << 32)) != 0L)
value32 = *from_ptr++;
if ((in_mask & (1L << 33)) != 0L)
value33 = *from_ptr++;
if ((in_mask & (1L << 34)) != 0L)
value34 = *from_ptr++;
if ((in_mask & (1L << 35)) != 0L)
value35 = *from_ptr++;
if ((in_mask & (1L << 36)) != 0L)
value36 = *from_ptr++;
if ((in_mask & (1L << 37)) != 0L)
value37 = *from_ptr++;
if ((in_mask & (1L << 38)) != 0L)
value38 = *from_ptr++;
if ((in_mask & (1L << 39)) != 0L)
value39 = *from_ptr++;
out_mask = *out_mask_ptr++;
if ((out_mask & (1L << 0)) != 0L)
*to_ptr++ = value00;
if ((out_mask & (1L << 1)) != 0L)
*to_ptr++ = value01;
if ((out_mask & (1L << 2)) != 0L)
*to_ptr++ = value02;
if ((out_mask & (1L << 3)) != 0L)
*to_ptr++ = value03;
if ((out_mask & (1L << 4)) != 0L)
*to_ptr++ = value04;
if ((out_mask & (1L << 5)) != 0L)
*to_ptr++ = value05;
if ((out_mask & (1L << 6)) != 0L)
*to_ptr++ = value06;
if ((out_mask & (1L << 7)) != 0L)
*to_ptr++ = value07;
if ((out_mask & (1L << 8)) != 0L)
*to_ptr++ = value08;
if ((out_mask & (1L << 9)) != 0L)
*to_ptr++ = value09;
if ((out_mask & (1L << 10)) != 0L)
*to_ptr++ = value10;
if ((out_mask & (1L << 11)) != 0L)
*to_ptr++ = value11;
if ((out_mask & (1L << 12)) != 0L)
*to_ptr++ = value12;
if ((out_mask & (1L << 13)) != 0L)
*to_ptr++ = value13;
if ((out_mask & (1L << 14)) != 0L)
*to_ptr++ = value14;
if ((out_mask & (1L << 15)) != 0L)
*to_ptr++ = value15;
if ((out_mask & (1L << 16)) != 0L)
*to_ptr++ = value16;
if ((out_mask & (1L << 17)) != 0L)
*to_ptr++ = value17;
if ((out_mask & (1L << 18)) != 0L)
*to_ptr++ = value18;
if ((out_mask & (1L << 19)) != 0L)
*to_ptr++ = value19;
if ((out_mask & (1L << 20)) != 0L)
*to_ptr++ = value20;
if ((out_mask & (1L << 21)) != 0L)
*to_ptr++ = value21;
if ((out_mask & (1L << 22)) != 0L)
*to_ptr++ = value22;
if ((out_mask & (1L << 23)) != 0L)
*to_ptr++ = value23;
if ((out_mask & (1L << 24)) != 0L)
*to_ptr++ = value24;
if ((out_mask & (1L << 25)) != 0L)
*to_ptr++ = value25;
if ((out_mask & (1L << 26)) != 0L)
*to_ptr++ = value26;
if ((out_mask & (1L << 27)) != 0L)
*to_ptr++ = value27;
if ((out_mask & (1L << 28)) != 0L)
*to_ptr++ = value28;
if ((out_mask & (1L << 29)) != 0L)
*to_ptr++ = value29;
if ((out_mask & (1L << 30)) != 0L)
*to_ptr++ = value30;
if ((out_mask & (1L << 31)) != 0L)
*to_ptr++ = value31;
if ((out_mask & (1L << 32)) != 0L)
*to_ptr++ = value32;
if ((out_mask & (1L << 33)) != 0L)
*to_ptr++ = value33;
if ((out_mask & (1L << 34)) != 0L)
*to_ptr++ = value34;
if ((out_mask & (1L << 35)) != 0L)
*to_ptr++ = value35;
if ((out_mask & (1L << 36)) != 0L)
*to_ptr++ = value36;
if ((out_mask & (1L << 37)) != 0L)
*to_ptr++ = value37;
if ((out_mask & (1L << 38)) != 0L)
*to_ptr++ = value38;
if ((out_mask & (1L << 39)) != 0L)
*to_ptr++ = value39;
}
return ( value00 + value01 + value02 + value03 + value04
+ value05 + value06 + value07 + value08 + value09
+ value10 + value11 + value12 + value13 + value14
+ value15 + value16 + value17 + value18 + value19
+ value20 + value21 + value22 + value23 + value24
+ value25 + value26 + value27 + value28 + value29
+ value30 + value31 + value32 + value33 + value34
+ value35 + value36 + value37 + value38 + value39);
}
/* { dg-final { scan-assembler "lxsspx" } } */
/* { dg-final { scan-assembler "lxsdx" } } */
/* { dg-final { scan-assembler "stxsspx" } } */
/* { dg-final { scan-assembler "stxsdx" } } */
/* { dg-final { scan-assembler "xsaddsp" } } */
/* { dg-final { scan-assembler "xsadddp" } } */

726
gcc/testsuite/gcc.target/powerpc/upper-regs-df.c Normal file
View File

@ -0,0 +1,726 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-options "-mcpu=power7 -O2 -mupper-regs-df" } */
/* Test for the -mupper-regs-df option to make sure double values are allocated
to the Altivec registers as well as the traditional FPR registers. */
#ifndef TYPE
#define TYPE double
#endif
#ifndef MASK_TYPE
#define MASK_TYPE unsigned long long
#endif
#define MASK_ONE ((MASK_TYPE)1)
#define ZERO ((TYPE) 0.0)
TYPE
test_add (const MASK_TYPE *add_mask, const TYPE *add_values,
const MASK_TYPE *sub_mask, const TYPE *sub_values,
const MASK_TYPE *mul_mask, const TYPE *mul_values,
const MASK_TYPE *div_mask, const TYPE *div_values,
const MASK_TYPE *eq0_mask, int *eq0_ptr)
{
TYPE value;
TYPE value00 = ZERO;
TYPE value01 = ZERO;
TYPE value02 = ZERO;
TYPE value03 = ZERO;
TYPE value04 = ZERO;
TYPE value05 = ZERO;
TYPE value06 = ZERO;
TYPE value07 = ZERO;
TYPE value08 = ZERO;
TYPE value09 = ZERO;
TYPE value10 = ZERO;
TYPE value11 = ZERO;
TYPE value12 = ZERO;
TYPE value13 = ZERO;
TYPE value14 = ZERO;
TYPE value15 = ZERO;
TYPE value16 = ZERO;
TYPE value17 = ZERO;
TYPE value18 = ZERO;
TYPE value19 = ZERO;
TYPE value20 = ZERO;
TYPE value21 = ZERO;
TYPE value22 = ZERO;
TYPE value23 = ZERO;
TYPE value24 = ZERO;
TYPE value25 = ZERO;
TYPE value26 = ZERO;
TYPE value27 = ZERO;
TYPE value28 = ZERO;
TYPE value29 = ZERO;
TYPE value30 = ZERO;
TYPE value31 = ZERO;
TYPE value32 = ZERO;
TYPE value33 = ZERO;
TYPE value34 = ZERO;
TYPE value35 = ZERO;
TYPE value36 = ZERO;
TYPE value37 = ZERO;
TYPE value38 = ZERO;
TYPE value39 = ZERO;
MASK_TYPE mask;
int eq0;
while ((mask = *add_mask++) != 0)
{
value = *add_values++;
__asm__ (" #reg %0" : "+d" (value));
if ((mask & (MASK_ONE << 0)) != 0)
value00 += value;
if ((mask & (MASK_ONE << 1)) != 0)
value01 += value;
if ((mask & (MASK_ONE << 2)) != 0)
value02 += value;
if ((mask & (MASK_ONE << 3)) != 0)
value03 += value;
if ((mask & (MASK_ONE << 4)) != 0)
value04 += value;
if ((mask & (MASK_ONE << 5)) != 0)
value05 += value;
if ((mask & (MASK_ONE << 6)) != 0)
value06 += value;
if ((mask & (MASK_ONE << 7)) != 0)
value07 += value;
if ((mask & (MASK_ONE << 8)) != 0)
value08 += value;
if ((mask & (MASK_ONE << 9)) != 0)
value09 += value;
if ((mask & (MASK_ONE << 10)) != 0)
value10 += value;
if ((mask & (MASK_ONE << 11)) != 0)
value11 += value;
if ((mask & (MASK_ONE << 12)) != 0)
value12 += value;
if ((mask & (MASK_ONE << 13)) != 0)
value13 += value;
if ((mask & (MASK_ONE << 14)) != 0)
value14 += value;
if ((mask & (MASK_ONE << 15)) != 0)
value15 += value;
if ((mask & (MASK_ONE << 16)) != 0)
value16 += value;
if ((mask & (MASK_ONE << 17)) != 0)
value17 += value;
if ((mask & (MASK_ONE << 18)) != 0)
value18 += value;
if ((mask & (MASK_ONE << 19)) != 0)
value19 += value;
if ((mask & (MASK_ONE << 20)) != 0)
value20 += value;
if ((mask & (MASK_ONE << 21)) != 0)
value21 += value;
if ((mask & (MASK_ONE << 22)) != 0)
value22 += value;
if ((mask & (MASK_ONE << 23)) != 0)
value23 += value;
if ((mask & (MASK_ONE << 24)) != 0)
value24 += value;
if ((mask & (MASK_ONE << 25)) != 0)
value25 += value;
if ((mask & (MASK_ONE << 26)) != 0)
value26 += value;
if ((mask & (MASK_ONE << 27)) != 0)
value27 += value;
if ((mask & (MASK_ONE << 28)) != 0)
value28 += value;
if ((mask & (MASK_ONE << 29)) != 0)
value29 += value;
if ((mask & (MASK_ONE << 30)) != 0)
value30 += value;
if ((mask & (MASK_ONE << 31)) != 0)
value31 += value;
if ((mask & (MASK_ONE << 32)) != 0)
value32 += value;
if ((mask & (MASK_ONE << 33)) != 0)
value33 += value;
if ((mask & (MASK_ONE << 34)) != 0)
value34 += value;
if ((mask & (MASK_ONE << 35)) != 0)
value35 += value;
if ((mask & (MASK_ONE << 36)) != 0)
value36 += value;
if ((mask & (MASK_ONE << 37)) != 0)
value37 += value;
if ((mask & (MASK_ONE << 38)) != 0)
value38 += value;
if ((mask & (MASK_ONE << 39)) != 0)
value39 += value;
}
while ((mask = *sub_mask++) != 0)
{
value = *sub_values++;
__asm__ (" #reg %0" : "+d" (value));
if ((mask & (MASK_ONE << 0)) != 0)
value00 -= value;
if ((mask & (MASK_ONE << 1)) != 0)
value01 -= value;
if ((mask & (MASK_ONE << 2)) != 0)
value02 -= value;
if ((mask & (MASK_ONE << 3)) != 0)
value03 -= value;
if ((mask & (MASK_ONE << 4)) != 0)
value04 -= value;
if ((mask & (MASK_ONE << 5)) != 0)
value05 -= value;
if ((mask & (MASK_ONE << 6)) != 0)
value06 -= value;
if ((mask & (MASK_ONE << 7)) != 0)
value07 -= value;
if ((mask & (MASK_ONE << 8)) != 0)
value08 -= value;
if ((mask & (MASK_ONE << 9)) != 0)
value09 -= value;
if ((mask & (MASK_ONE << 10)) != 0)
value10 -= value;
if ((mask & (MASK_ONE << 11)) != 0)
value11 -= value;
if ((mask & (MASK_ONE << 12)) != 0)
value12 -= value;
if ((mask & (MASK_ONE << 13)) != 0)
value13 -= value;
if ((mask & (MASK_ONE << 14)) != 0)
value14 -= value;
if ((mask & (MASK_ONE << 15)) != 0)
value15 -= value;
if ((mask & (MASK_ONE << 16)) != 0)
value16 -= value;
if ((mask & (MASK_ONE << 17)) != 0)
value17 -= value;
if ((mask & (MASK_ONE << 18)) != 0)
value18 -= value;
if ((mask & (MASK_ONE << 19)) != 0)
value19 -= value;
if ((mask & (MASK_ONE << 20)) != 0)
value20 -= value;
if ((mask & (MASK_ONE << 21)) != 0)
value21 -= value;
if ((mask & (MASK_ONE << 22)) != 0)
value22 -= value;
if ((mask & (MASK_ONE << 23)) != 0)
value23 -= value;
if ((mask & (MASK_ONE << 24)) != 0)
value24 -= value;
if ((mask & (MASK_ONE << 25)) != 0)
value25 -= value;
if ((mask & (MASK_ONE << 26)) != 0)
value26 -= value;
if ((mask & (MASK_ONE << 27)) != 0)
value27 -= value;
if ((mask & (MASK_ONE << 28)) != 0)
value28 -= value;
if ((mask & (MASK_ONE << 29)) != 0)
value29 -= value;
if ((mask & (MASK_ONE << 30)) != 0)
value30 -= value;
if ((mask & (MASK_ONE << 31)) != 0)
value31 -= value;
if ((mask & (MASK_ONE << 32)) != 0)
value32 -= value;
if ((mask & (MASK_ONE << 33)) != 0)
value33 -= value;
if ((mask & (MASK_ONE << 34)) != 0)
value34 -= value;
if ((mask & (MASK_ONE << 35)) != 0)
value35 -= value;
if ((mask & (MASK_ONE << 36)) != 0)
value36 -= value;
if ((mask & (MASK_ONE << 37)) != 0)
value37 -= value;
if ((mask & (MASK_ONE << 38)) != 0)
value38 -= value;
if ((mask & (MASK_ONE << 39)) != 0)
value39 -= value;
}
while ((mask = *mul_mask++) != 0)
{
value = *mul_values++;
__asm__ (" #reg %0" : "+d" (value));
if ((mask & (MASK_ONE << 0)) != 0)
value00 *= value;
if ((mask & (MASK_ONE << 1)) != 0)
value01 *= value;
if ((mask & (MASK_ONE << 2)) != 0)
value02 *= value;
if ((mask & (MASK_ONE << 3)) != 0)
value03 *= value;
if ((mask & (MASK_ONE << 4)) != 0)
value04 *= value;
if ((mask & (MASK_ONE << 5)) != 0)
value05 *= value;
if ((mask & (MASK_ONE << 6)) != 0)
value06 *= value;
if ((mask & (MASK_ONE << 7)) != 0)
value07 *= value;
if ((mask & (MASK_ONE << 8)) != 0)
value08 *= value;
if ((mask & (MASK_ONE << 9)) != 0)
value09 *= value;
if ((mask & (MASK_ONE << 10)) != 0)
value10 *= value;
if ((mask & (MASK_ONE << 11)) != 0)
value11 *= value;
if ((mask & (MASK_ONE << 12)) != 0)
value12 *= value;
if ((mask & (MASK_ONE << 13)) != 0)
value13 *= value;
if ((mask & (MASK_ONE << 14)) != 0)
value14 *= value;
if ((mask & (MASK_ONE << 15)) != 0)
value15 *= value;
if ((mask & (MASK_ONE << 16)) != 0)
value16 *= value;
if ((mask & (MASK_ONE << 17)) != 0)
value17 *= value;
if ((mask & (MASK_ONE << 18)) != 0)
value18 *= value;
if ((mask & (MASK_ONE << 19)) != 0)
value19 *= value;
if ((mask & (MASK_ONE << 20)) != 0)
value20 *= value;
if ((mask & (MASK_ONE << 21)) != 0)
value21 *= value;
if ((mask & (MASK_ONE << 22)) != 0)
value22 *= value;
if ((mask & (MASK_ONE << 23)) != 0)
value23 *= value;
if ((mask & (MASK_ONE << 24)) != 0)
value24 *= value;
if ((mask & (MASK_ONE << 25)) != 0)
value25 *= value;
if ((mask & (MASK_ONE << 26)) != 0)
value26 *= value;
if ((mask & (MASK_ONE << 27)) != 0)
value27 *= value;
if ((mask & (MASK_ONE << 28)) != 0)
value28 *= value;
if ((mask & (MASK_ONE << 29)) != 0)
value29 *= value;
if ((mask & (MASK_ONE << 30)) != 0)
value30 *= value;
if ((mask & (MASK_ONE << 31)) != 0)
value31 *= value;
if ((mask & (MASK_ONE << 32)) != 0)
value32 *= value;
if ((mask & (MASK_ONE << 33)) != 0)
value33 *= value;
if ((mask & (MASK_ONE << 34)) != 0)
value34 *= value;
if ((mask & (MASK_ONE << 35)) != 0)
value35 *= value;
if ((mask & (MASK_ONE << 36)) != 0)
value36 *= value;
if ((mask & (MASK_ONE << 37)) != 0)
value37 *= value;
if ((mask & (MASK_ONE << 38)) != 0)
value38 *= value;
if ((mask & (MASK_ONE << 39)) != 0)
value39 *= value;
}
while ((mask = *div_mask++) != 0)
{
value = *div_values++;
__asm__ (" #reg %0" : "+d" (value));
if ((mask & (MASK_ONE << 0)) != 0)
value00 /= value;
if ((mask & (MASK_ONE << 1)) != 0)
value01 /= value;
if ((mask & (MASK_ONE << 2)) != 0)
value02 /= value;
if ((mask & (MASK_ONE << 3)) != 0)
value03 /= value;
if ((mask & (MASK_ONE << 4)) != 0)
value04 /= value;
if ((mask & (MASK_ONE << 5)) != 0)
value05 /= value;
if ((mask & (MASK_ONE << 6)) != 0)
value06 /= value;
if ((mask & (MASK_ONE << 7)) != 0)
value07 /= value;
if ((mask & (MASK_ONE << 8)) != 0)
value08 /= value;
if ((mask & (MASK_ONE << 9)) != 0)
value09 /= value;
if ((mask & (MASK_ONE << 10)) != 0)
value10 /= value;
if ((mask & (MASK_ONE << 11)) != 0)
value11 /= value;
if ((mask & (MASK_ONE << 12)) != 0)
value12 /= value;
if ((mask & (MASK_ONE << 13)) != 0)
value13 /= value;
if ((mask & (MASK_ONE << 14)) != 0)
value14 /= value;
if ((mask & (MASK_ONE << 15)) != 0)
value15 /= value;
if ((mask & (MASK_ONE << 16)) != 0)
value16 /= value;
if ((mask & (MASK_ONE << 17)) != 0)
value17 /= value;
if ((mask & (MASK_ONE << 18)) != 0)
value18 /= value;
if ((mask & (MASK_ONE << 19)) != 0)
value19 /= value;
if ((mask & (MASK_ONE << 20)) != 0)
value20 /= value;
if ((mask & (MASK_ONE << 21)) != 0)
value21 /= value;
if ((mask & (MASK_ONE << 22)) != 0)
value22 /= value;
if ((mask & (MASK_ONE << 23)) != 0)
value23 /= value;
if ((mask & (MASK_ONE << 24)) != 0)
value24 /= value;
if ((mask & (MASK_ONE << 25)) != 0)
value25 /= value;
if ((mask & (MASK_ONE << 26)) != 0)
value26 /= value;
if ((mask & (MASK_ONE << 27)) != 0)
value27 /= value;
if ((mask & (MASK_ONE << 28)) != 0)
value28 /= value;
if ((mask & (MASK_ONE << 29)) != 0)
value29 /= value;
if ((mask & (MASK_ONE << 30)) != 0)
value30 /= value;
if ((mask & (MASK_ONE << 31)) != 0)
value31 /= value;
if ((mask & (MASK_ONE << 32)) != 0)
value32 /= value;
if ((mask & (MASK_ONE << 33)) != 0)
value33 /= value;
if ((mask & (MASK_ONE << 34)) != 0)
value34 /= value;
if ((mask & (MASK_ONE << 35)) != 0)
value35 /= value;
if ((mask & (MASK_ONE << 36)) != 0)
value36 /= value;
if ((mask & (MASK_ONE << 37)) != 0)
value37 /= value;
if ((mask & (MASK_ONE << 38)) != 0)
value38 /= value;
if ((mask & (MASK_ONE << 39)) != 0)
value39 /= value;
}
while ((mask = *eq0_mask++) != 0)
{
eq0 = 0;
if ((mask & (MASK_ONE << 0)) != 0)
eq0 |= (value00 == ZERO);
if ((mask & (MASK_ONE << 1)) != 0)
eq0 |= (value01 == ZERO);
if ((mask & (MASK_ONE << 2)) != 0)
eq0 |= (value02 == ZERO);
if ((mask & (MASK_ONE << 3)) != 0)
eq0 |= (value03 == ZERO);
if ((mask & (MASK_ONE << 4)) != 0)
eq0 |= (value04 == ZERO);
if ((mask & (MASK_ONE << 5)) != 0)
eq0 |= (value05 == ZERO);
if ((mask & (MASK_ONE << 6)) != 0)
eq0 |= (value06 == ZERO);
if ((mask & (MASK_ONE << 7)) != 0)
eq0 |= (value07 == ZERO);
if ((mask & (MASK_ONE << 8)) != 0)
eq0 |= (value08 == ZERO);
if ((mask & (MASK_ONE << 9)) != 0)
eq0 |= (value09 == ZERO);
if ((mask & (MASK_ONE << 10)) != 0)
eq0 |= (value10 == ZERO);
if ((mask & (MASK_ONE << 11)) != 0)
eq0 |= (value11 == ZERO);
if ((mask & (MASK_ONE << 12)) != 0)
eq0 |= (value12 == ZERO);
if ((mask & (MASK_ONE << 13)) != 0)
eq0 |= (value13 == ZERO);
if ((mask & (MASK_ONE << 14)) != 0)
eq0 |= (value14 == ZERO);
if ((mask & (MASK_ONE << 15)) != 0)
eq0 |= (value15 == ZERO);
if ((mask & (MASK_ONE << 16)) != 0)
eq0 |= (value16 == ZERO);
if ((mask & (MASK_ONE << 17)) != 0)
eq0 |= (value17 == ZERO);
if ((mask & (MASK_ONE << 18)) != 0)
eq0 |= (value18 == ZERO);
if ((mask & (MASK_ONE << 19)) != 0)
eq0 |= (value19 == ZERO);
if ((mask & (MASK_ONE << 20)) != 0)
eq0 |= (value20 == ZERO);
if ((mask & (MASK_ONE << 21)) != 0)
eq0 |= (value21 == ZERO);
if ((mask & (MASK_ONE << 22)) != 0)
eq0 |= (value22 == ZERO);
if ((mask & (MASK_ONE << 23)) != 0)
eq0 |= (value23 == ZERO);
if ((mask & (MASK_ONE << 24)) != 0)
eq0 |= (value24 == ZERO);
if ((mask & (MASK_ONE << 25)) != 0)
eq0 |= (value25 == ZERO);
if ((mask & (MASK_ONE << 26)) != 0)
eq0 |= (value26 == ZERO);
if ((mask & (MASK_ONE << 27)) != 0)
eq0 |= (value27 == ZERO);
if ((mask & (MASK_ONE << 28)) != 0)
eq0 |= (value28 == ZERO);
if ((mask & (MASK_ONE << 29)) != 0)
eq0 |= (value29 == ZERO);
if ((mask & (MASK_ONE << 30)) != 0)
eq0 |= (value30 == ZERO);
if ((mask & (MASK_ONE << 31)) != 0)
eq0 |= (value31 == ZERO);
if ((mask & (MASK_ONE << 32)) != 0)
eq0 |= (value32 == ZERO);
if ((mask & (MASK_ONE << 33)) != 0)
eq0 |= (value33 == ZERO);
if ((mask & (MASK_ONE << 34)) != 0)
eq0 |= (value34 == ZERO);
if ((mask & (MASK_ONE << 35)) != 0)
eq0 |= (value35 == ZERO);
if ((mask & (MASK_ONE << 36)) != 0)
eq0 |= (value36 == ZERO);
if ((mask & (MASK_ONE << 37)) != 0)
eq0 |= (value37 == ZERO);
if ((mask & (MASK_ONE << 38)) != 0)
eq0 |= (value38 == ZERO);
if ((mask & (MASK_ONE << 39)) != 0)
eq0 |= (value39 == ZERO);
*eq0_ptr++ = eq0;
}
return ( value00 + value01 + value02 + value03 + value04
+ value05 + value06 + value07 + value08 + value09
+ value10 + value11 + value12 + value13 + value14
+ value15 + value16 + value17 + value18 + value19
+ value20 + value21 + value22 + value23 + value24
+ value25 + value26 + value27 + value28 + value29
+ value30 + value31 + value32 + value33 + value34
+ value35 + value36 + value37 + value38 + value39);
}
/* { dg-final { scan-assembler "fadd" } } */
/* { dg-final { scan-assembler "fsub" } } */
/* { dg-final { scan-assembler "fmul" } } */
/* { dg-final { scan-assembler "fdiv" } } */
/* { dg-final { scan-assembler "fcmpu" } } */
/* { dg-final { scan-assembler "xsadddp" } } */
/* { dg-final { scan-assembler "xssubdp" } } */
/* { dg-final { scan-assembler "xsmuldp" } } */
/* { dg-final { scan-assembler "xsdivdp" } } */
/* { dg-final { scan-assembler "xscmpudp" } } */

726
gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c Normal file
View File

@ -0,0 +1,726 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */
/* Test for the -mupper-regs-df option to make sure double values are allocated
to the Altivec registers as well as the traditional FPR registers. */
#ifndef TYPE
#define TYPE float
#endif
#ifndef MASK_TYPE
#define MASK_TYPE unsigned long long
#endif
#define MASK_ONE ((MASK_TYPE)1)
#define ZERO ((TYPE) 0.0)
TYPE
test_add (const MASK_TYPE *add_mask, const TYPE *add_values,
const MASK_TYPE *sub_mask, const TYPE *sub_values,
const MASK_TYPE *mul_mask, const TYPE *mul_values,
const MASK_TYPE *div_mask, const TYPE *div_values,
const MASK_TYPE *eq0_mask, int *eq0_ptr)
{
TYPE value;
TYPE value00 = ZERO;
TYPE value01 = ZERO;
TYPE value02 = ZERO;
TYPE value03 = ZERO;
TYPE value04 = ZERO;
TYPE value05 = ZERO;
TYPE value06 = ZERO;
TYPE value07 = ZERO;
TYPE value08 = ZERO;
TYPE value09 = ZERO;
TYPE value10 = ZERO;
TYPE value11 = ZERO;
TYPE value12 = ZERO;
TYPE value13 = ZERO;
TYPE value14 = ZERO;
TYPE value15 = ZERO;
TYPE value16 = ZERO;
TYPE value17 = ZERO;
TYPE value18 = ZERO;
TYPE value19 = ZERO;
TYPE value20 = ZERO;
TYPE value21 = ZERO;
TYPE value22 = ZERO;
TYPE value23 = ZERO;
TYPE value24 = ZERO;
TYPE value25 = ZERO;
TYPE value26 = ZERO;
TYPE value27 = ZERO;
TYPE value28 = ZERO;
TYPE value29 = ZERO;
TYPE value30 = ZERO;
TYPE value31 = ZERO;
TYPE value32 = ZERO;
TYPE value33 = ZERO;
TYPE value34 = ZERO;
TYPE value35 = ZERO;
TYPE value36 = ZERO;
TYPE value37 = ZERO;
TYPE value38 = ZERO;
TYPE value39 = ZERO;
MASK_TYPE mask;
int eq0;
while ((mask = *add_mask++) != 0)
{
value = *add_values++;
__asm__ (" #reg %0" : "+d" (value));
if ((mask & (MASK_ONE << 0)) != 0)
value00 += value;
if ((mask & (MASK_ONE << 1)) != 0)
value01 += value;
if ((mask & (MASK_ONE << 2)) != 0)
value02 += value;
if ((mask & (MASK_ONE << 3)) != 0)
value03 += value;
if ((mask & (MASK_ONE << 4)) != 0)
value04 += value;
if ((mask & (MASK_ONE << 5)) != 0)
value05 += value;
if ((mask & (MASK_ONE << 6)) != 0)
value06 += value;
if ((mask & (MASK_ONE << 7)) != 0)
value07 += value;
if ((mask & (MASK_ONE << 8)) != 0)
value08 += value;
if ((mask & (MASK_ONE << 9)) != 0)
value09 += value;
if ((mask & (MASK_ONE << 10)) != 0)
value10 += value;
if ((mask & (MASK_ONE << 11)) != 0)
value11 += value;
if ((mask & (MASK_ONE << 12)) != 0)
value12 += value;
if ((mask & (MASK_ONE << 13)) != 0)
value13 += value;
if ((mask & (MASK_ONE << 14)) != 0)
value14 += value;
if ((mask & (MASK_ONE << 15)) != 0)
value15 += value;
if ((mask & (MASK_ONE << 16)) != 0)
value16 += value;
if ((mask & (MASK_ONE << 17)) != 0)
value17 += value;
if ((mask & (MASK_ONE << 18)) != 0)
value18 += value;
if ((mask & (MASK_ONE << 19)) != 0)
value19 += value;
if ((mask & (MASK_ONE << 20)) != 0)
value20 += value;
if ((mask & (MASK_ONE << 21)) != 0)
value21 += value;
if ((mask & (MASK_ONE << 22)) != 0)
value22 += value;
if ((mask & (MASK_ONE << 23)) != 0)
value23 += value;
if ((mask & (MASK_ONE << 24)) != 0)
value24 += value;
if ((mask & (MASK_ONE << 25)) != 0)
value25 += value;
if ((mask & (MASK_ONE << 26)) != 0)
value26 += value;
if ((mask & (MASK_ONE << 27)) != 0)
value27 += value;
if ((mask & (MASK_ONE << 28)) != 0)
value28 += value;
if ((mask & (MASK_ONE << 29)) != 0)
value29 += value;
if ((mask & (MASK_ONE << 30)) != 0)
value30 += value;
if ((mask & (MASK_ONE << 31)) != 0)
value31 += value;
if ((mask & (MASK_ONE << 32)) != 0)
value32 += value;
if ((mask & (MASK_ONE << 33)) != 0)
value33 += value;
if ((mask & (MASK_ONE << 34)) != 0)
value34 += value;
if ((mask & (MASK_ONE << 35)) != 0)
value35 += value;
if ((mask & (MASK_ONE << 36)) != 0)
value36 += value;
if ((mask & (MASK_ONE << 37)) != 0)
value37 += value;
if ((mask & (MASK_ONE << 38)) != 0)
value38 += value;
if ((mask & (MASK_ONE << 39)) != 0)
value39 += value;
}
while ((mask = *sub_mask++) != 0)
{
value = *sub_values++;
__asm__ (" #reg %0" : "+d" (value));
if ((mask & (MASK_ONE << 0)) != 0)
value00 -= value;
if ((mask & (MASK_ONE << 1)) != 0)
value01 -= value;
if ((mask & (MASK_ONE << 2)) != 0)
value02 -= value;
if ((mask & (MASK_ONE << 3)) != 0)
value03 -= value;
if ((mask & (MASK_ONE << 4)) != 0)
value04 -= value;
if ((mask & (MASK_ONE << 5)) != 0)
value05 -= value;
if ((mask & (MASK_ONE << 6)) != 0)
value06 -= value;
if ((mask & (MASK_ONE << 7)) != 0)
value07 -= value;
if ((mask & (MASK_ONE << 8)) != 0)
value08 -= value;
if ((mask & (MASK_ONE << 9)) != 0)
value09 -= value;
if ((mask & (MASK_ONE << 10)) != 0)
value10 -= value;
if ((mask & (MASK_ONE << 11)) != 0)
value11 -= value;
if ((mask & (MASK_ONE << 12)) != 0)
value12 -= value;
if ((mask & (MASK_ONE << 13)) != 0)
value13 -= value;
if ((mask & (MASK_ONE << 14)) != 0)
value14 -= value;
if ((mask & (MASK_ONE << 15)) != 0)
value15 -= value;
if ((mask & (MASK_ONE << 16)) != 0)
value16 -= value;
if ((mask & (MASK_ONE << 17)) != 0)
value17 -= value;
if ((mask & (MASK_ONE << 18)) != 0)
value18 -= value;
if ((mask & (MASK_ONE << 19)) != 0)
value19 -= value;
if ((mask & (MASK_ONE << 20)) != 0)
value20 -= value;
if ((mask & (MASK_ONE << 21)) != 0)
value21 -= value;
if ((mask & (MASK_ONE << 22)) != 0)
value22 -= value;
if ((mask & (MASK_ONE << 23)) != 0)
value23 -= value;
if ((mask & (MASK_ONE << 24)) != 0)
value24 -= value;
if ((mask & (MASK_ONE << 25)) != 0)
value25 -= value;
if ((mask & (MASK_ONE << 26)) != 0)
value26 -= value;
if ((mask & (MASK_ONE << 27)) != 0)
value27 -= value;
if ((mask & (MASK_ONE << 28)) != 0)
value28 -= value;
if ((mask & (MASK_ONE << 29)) != 0)
value29 -= value;
if ((mask & (MASK_ONE << 30)) != 0)
value30 -= value;
if ((mask & (MASK_ONE << 31)) != 0)
value31 -= value;
if ((mask & (MASK_ONE << 32)) != 0)
value32 -= value;
if ((mask & (MASK_ONE << 33)) != 0)
value33 -= value;
if ((mask & (MASK_ONE << 34)) != 0)
value34 -= value;
if ((mask & (MASK_ONE << 35)) != 0)
value35 -= value;
if ((mask & (MASK_ONE << 36)) != 0)
value36 -= value;
if ((mask & (MASK_ONE << 37)) != 0)
value37 -= value;
if ((mask & (MASK_ONE << 38)) != 0)
value38 -= value;
if ((mask & (MASK_ONE << 39)) != 0)
value39 -= value;
}
while ((mask = *mul_mask++) != 0)
{
value = *mul_values++;
__asm__ (" #reg %0" : "+d" (value));
if ((mask & (MASK_ONE << 0)) != 0)
value00 *= value;
if ((mask & (MASK_ONE << 1)) != 0)
value01 *= value;
if ((mask & (MASK_ONE << 2)) != 0)
value02 *= value;
if ((mask & (MASK_ONE << 3)) != 0)
value03 *= value;
if ((mask & (MASK_ONE << 4)) != 0)
value04 *= value;
if ((mask & (MASK_ONE << 5)) != 0)
value05 *= value;
if ((mask & (MASK_ONE << 6)) != 0)
value06 *= value;
if ((mask & (MASK_ONE << 7)) != 0)
value07 *= value;
if ((mask & (MASK_ONE << 8)) != 0)
value08 *= value;
if ((mask & (MASK_ONE << 9)) != 0)
value09 *= value;
if ((mask & (MASK_ONE << 10)) != 0)
value10 *= value;
if ((mask & (MASK_ONE << 11)) != 0)
value11 *= value;
if ((mask & (MASK_ONE << 12)) != 0)
value12 *= value;
if ((mask & (MASK_ONE << 13)) != 0)
value13 *= value;
if ((mask & (MASK_ONE << 14)) != 0)
value14 *= value;
if ((mask & (MASK_ONE << 15)) != 0)
value15 *= value;
if ((mask & (MASK_ONE << 16)) != 0)
value16 *= value;
if ((mask & (MASK_ONE << 17)) != 0)
value17 *= value;
if ((mask & (MASK_ONE << 18)) != 0)
value18 *= value;
if ((mask & (MASK_ONE << 19)) != 0)
value19 *= value;
if ((mask & (MASK_ONE << 20)) != 0)
value20 *= value;
if ((mask & (MASK_ONE << 21)) != 0)
value21 *= value;
if ((mask & (MASK_ONE << 22)) != 0)
value22 *= value;
if ((mask & (MASK_ONE << 23)) != 0)
value23 *= value;
if ((mask & (MASK_ONE << 24)) != 0)
value24 *= value;
if ((mask & (MASK_ONE << 25)) != 0)
value25 *= value;
if ((mask & (MASK_ONE << 26)) != 0)
value26 *= value;
if ((mask & (MASK_ONE << 27)) != 0)
value27 *= value;
if ((mask & (MASK_ONE << 28)) != 0)
value28 *= value;
if ((mask & (MASK_ONE << 29)) != 0)
value29 *= value;
if ((mask & (MASK_ONE << 30)) != 0)
value30 *= value;
if ((mask & (MASK_ONE << 31)) != 0)
value31 *= value;
if ((mask & (MASK_ONE << 32)) != 0)
value32 *= value;
if ((mask & (MASK_ONE << 33)) != 0)
value33 *= value;
if ((mask & (MASK_ONE << 34)) != 0)
value34 *= value;
if ((mask & (MASK_ONE << 35)) != 0)
value35 *= value;
if ((mask & (MASK_ONE << 36)) != 0)
value36 *= value;
if ((mask & (MASK_ONE << 37)) != 0)
value37 *= value;
if ((mask & (MASK_ONE << 38)) != 0)
value38 *= value;
if ((mask & (MASK_ONE << 39)) != 0)
value39 *= value;
}
while ((mask = *div_mask++) != 0)
{
value = *div_values++;
__asm__ (" #reg %0" : "+d" (value));
if ((mask & (MASK_ONE << 0)) != 0)
value00 /= value;
if ((mask & (MASK_ONE << 1)) != 0)
value01 /= value;
if ((mask & (MASK_ONE << 2)) != 0)
value02 /= value;
if ((mask & (MASK_ONE << 3)) != 0)
value03 /= value;
if ((mask & (MASK_ONE << 4)) != 0)
value04 /= value;
if ((mask & (MASK_ONE << 5)) != 0)
value05 /= value;
if ((mask & (MASK_ONE << 6)) != 0)
value06 /= value;
if ((mask & (MASK_ONE << 7)) != 0)
value07 /= value;
if ((mask & (MASK_ONE << 8)) != 0)
value08 /= value;
if ((mask & (MASK_ONE << 9)) != 0)
value09 /= value;
if ((mask & (MASK_ONE << 10)) != 0)
value10 /= value;
if ((mask & (MASK_ONE << 11)) != 0)
value11 /= value;
if ((mask & (MASK_ONE << 12)) != 0)
value12 /= value;
if ((mask & (MASK_ONE << 13)) != 0)
value13 /= value;
if ((mask & (MASK_ONE << 14)) != 0)
value14 /= value;
if ((mask & (MASK_ONE << 15)) != 0)
value15 /= value;
if ((mask & (MASK_ONE << 16)) != 0)
value16 /= value;
if ((mask & (MASK_ONE << 17)) != 0)
value17 /= value;
if ((mask & (MASK_ONE << 18)) != 0)
value18 /= value;
if ((mask & (MASK_ONE << 19)) != 0)
value19 /= value;
if ((mask & (MASK_ONE << 20)) != 0)
value20 /= value;
if ((mask & (MASK_ONE << 21)) != 0)
value21 /= value;
if ((mask & (MASK_ONE << 22)) != 0)
value22 /= value;
if ((mask & (MASK_ONE << 23)) != 0)
value23 /= value;
if ((mask & (MASK_ONE << 24)) != 0)
value24 /= value;
if ((mask & (MASK_ONE << 25)) != 0)
value25 /= value;
if ((mask & (MASK_ONE << 26)) != 0)
value26 /= value;
if ((mask & (MASK_ONE << 27)) != 0)
value27 /= value;
if ((mask & (MASK_ONE << 28)) != 0)
value28 /= value;
if ((mask & (MASK_ONE << 29)) != 0)
value29 /= value;
if ((mask & (MASK_ONE << 30)) != 0)
value30 /= value;
if ((mask & (MASK_ONE << 31)) != 0)
value31 /= value;
if ((mask & (MASK_ONE << 32)) != 0)
value32 /= value;
if ((mask & (MASK_ONE << 33)) != 0)
value33 /= value;
if ((mask & (MASK_ONE << 34)) != 0)
value34 /= value;
if ((mask & (MASK_ONE << 35)) != 0)
value35 /= value;
if ((mask & (MASK_ONE << 36)) != 0)
value36 /= value;
if ((mask & (MASK_ONE << 37)) != 0)
value37 /= value;
if ((mask & (MASK_ONE << 38)) != 0)
value38 /= value;
if ((mask & (MASK_ONE << 39)) != 0)
value39 /= value;
}
while ((mask = *eq0_mask++) != 0)
{
eq0 = 0;
if ((mask & (MASK_ONE << 0)) != 0)
eq0 |= (value00 == ZERO);
if ((mask & (MASK_ONE << 1)) != 0)
eq0 |= (value01 == ZERO);
if ((mask & (MASK_ONE << 2)) != 0)
eq0 |= (value02 == ZERO);
if ((mask & (MASK_ONE << 3)) != 0)
eq0 |= (value03 == ZERO);
if ((mask & (MASK_ONE << 4)) != 0)
eq0 |= (value04 == ZERO);
if ((mask & (MASK_ONE << 5)) != 0)
eq0 |= (value05 == ZERO);
if ((mask & (MASK_ONE << 6)) != 0)
eq0 |= (value06 == ZERO);
if ((mask & (MASK_ONE << 7)) != 0)
eq0 |= (value07 == ZERO);
if ((mask & (MASK_ONE << 8)) != 0)
eq0 |= (value08 == ZERO);
if ((mask & (MASK_ONE << 9)) != 0)
eq0 |= (value09 == ZERO);
if ((mask & (MASK_ONE << 10)) != 0)
eq0 |= (value10 == ZERO);
if ((mask & (MASK_ONE << 11)) != 0)
eq0 |= (value11 == ZERO);
if ((mask & (MASK_ONE << 12)) != 0)
eq0 |= (value12 == ZERO);
if ((mask & (MASK_ONE << 13)) != 0)
eq0 |= (value13 == ZERO);
if ((mask & (MASK_ONE << 14)) != 0)
eq0 |= (value14 == ZERO);
if ((mask & (MASK_ONE << 15)) != 0)
eq0 |= (value15 == ZERO);
if ((mask & (MASK_ONE << 16)) != 0)
eq0 |= (value16 == ZERO);
if ((mask & (MASK_ONE << 17)) != 0)
eq0 |= (value17 == ZERO);
if ((mask & (MASK_ONE << 18)) != 0)
eq0 |= (value18 == ZERO);
if ((mask & (MASK_ONE << 19)) != 0)
eq0 |= (value19 == ZERO);
if ((mask & (MASK_ONE << 20)) != 0)
eq0 |= (value20 == ZERO);
if ((mask & (MASK_ONE << 21)) != 0)
eq0 |= (value21 == ZERO);
if ((mask & (MASK_ONE << 22)) != 0)
eq0 |= (value22 == ZERO);
if ((mask & (MASK_ONE << 23)) != 0)
eq0 |= (value23 == ZERO);
if ((mask & (MASK_ONE << 24)) != 0)
eq0 |= (value24 == ZERO);
if ((mask & (MASK_ONE << 25)) != 0)
eq0 |= (value25 == ZERO);
if ((mask & (MASK_ONE << 26)) != 0)
eq0 |= (value26 == ZERO);
if ((mask & (MASK_ONE << 27)) != 0)
eq0 |= (value27 == ZERO);
if ((mask & (MASK_ONE << 28)) != 0)
eq0 |= (value28 == ZERO);
if ((mask & (MASK_ONE << 29)) != 0)
eq0 |= (value29 == ZERO);
if ((mask & (MASK_ONE << 30)) != 0)
eq0 |= (value30 == ZERO);
if ((mask & (MASK_ONE << 31)) != 0)
eq0 |= (value31 == ZERO);
if ((mask & (MASK_ONE << 32)) != 0)
eq0 |= (value32 == ZERO);
if ((mask & (MASK_ONE << 33)) != 0)
eq0 |= (value33 == ZERO);
if ((mask & (MASK_ONE << 34)) != 0)
eq0 |= (value34 == ZERO);
if ((mask & (MASK_ONE << 35)) != 0)
eq0 |= (value35 == ZERO);
if ((mask & (MASK_ONE << 36)) != 0)
eq0 |= (value36 == ZERO);
if ((mask & (MASK_ONE << 37)) != 0)
eq0 |= (value37 == ZERO);
if ((mask & (MASK_ONE << 38)) != 0)
eq0 |= (value38 == ZERO);
if ((mask & (MASK_ONE << 39)) != 0)
eq0 |= (value39 == ZERO);
*eq0_ptr++ = eq0;
}
return ( value00 + value01 + value02 + value03 + value04
+ value05 + value06 + value07 + value08 + value09
+ value10 + value11 + value12 + value13 + value14
+ value15 + value16 + value17 + value18 + value19
+ value20 + value21 + value22 + value23 + value24
+ value25 + value26 + value27 + value28 + value29
+ value30 + value31 + value32 + value33 + value34
+ value35 + value36 + value37 + value38 + value39);
}
/* { dg-final { scan-assembler "fadds" } } */
/* { dg-final { scan-assembler "fsubs" } } */
/* { dg-final { scan-assembler "fmuls" } } */
/* { dg-final { scan-assembler "fdivs" } } */
/* { dg-final { scan-assembler "fcmpu" } } */
/* { dg-final { scan-assembler "xsaddsp" } } */
/* { dg-final { scan-assembler "xssubsp" } } */
/* { dg-final { scan-assembler "xsmulsp" } } */
/* { dg-final { scan-assembler "xsdivsp" } } */
/* { dg-final { scan-assembler "xscmpudp" } } */