AVX512FP16: Add float(uns)?mn2 expander

gcc/ChangeLog:

	* config/i386/sse.md (float<floatunssuffix><mode><ssePHmodelower>2):
	New expander.
	(avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>):
	Rename to ...
	(float<floatunssuffix><mode>v4hf2): ... this, and drop constraints.
	(avx512fp16_vcvt<floatsuffix>qq2ph_v2di): Rename to ...
	(float<floatunssuffix>v2div2hf2): ... this, and likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx512fp16-floatvnhf.c: New test.
This commit is contained in:
Hongyu Wang 2021-07-12 09:45:33 +08:00 committed by liuhongt
parent 60698a19c7
commit 25faed6f37
2 changed files with 99 additions and 8 deletions
gcc
config/i386
testsuite/gcc.target/i386

@ -6006,6 +6006,12 @@
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
(define_expand "float<floatunssuffix><mode><ssePHmodelower>2"
[(set (match_operand:<ssePHmode> 0 "register_operand")
(any_float:<ssePHmode>
(match_operand:VI2H_AVX512VL 1 "nonimmediate_operand")))]
"TARGET_AVX512FP16")
(define_insn "avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode><mask_name><round_name>"
[(set (match_operand:<ssePHmode> 0 "register_operand" "=v")
(any_float:<ssePHmode>
@ -6016,11 +6022,23 @@
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
(define_expand "avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>"
[(set (match_operand:V8HF 0 "register_operand" "=v")
(define_expand "float<floatunssuffix><mode>v4hf2"
[(set (match_operand:V4HF 0 "register_operand")
(any_float:V4HF
(match_operand:VI4_128_8_256 1 "vector_operand")))]
"TARGET_AVX512FP16 && TARGET_AVX512VL"
{
operands[0] = lowpart_subreg (V8HFmode, operands[0], V4HFmode);
emit_insn (gen_avx512fp16_float<floatunssuffix><mode>v4hf2 (operands[0],
operands[1]));
DONE;
})
(define_expand "avx512fp16_float<floatunssuffix><mode>v4hf2"
[(set (match_operand:V8HF 0 "register_operand")
(vec_concat:V8HF
(any_float:V4HF (match_operand:VI4_128_8_256 1 "vector_operand" "vm"))
(match_dup 2)))]
(any_float:V4HF (match_operand:VI4_128_8_256 1 "vector_operand"))
(match_dup 2)))]
"TARGET_AVX512FP16 && TARGET_AVX512VL"
"operands[2] = CONST0_RTX (V4HFmode);")
@ -6079,11 +6097,23 @@
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
(define_expand "avx512fp16_vcvt<floatsuffix>qq2ph_v2di"
[(set (match_operand:V8HF 0 "register_operand" "=v")
(define_expand "float<floatunssuffix>v2div2hf2"
[(set (match_operand:V2HF 0 "register_operand")
(any_float:V2HF
(match_operand:V2DI 1 "vector_operand")))]
"TARGET_AVX512FP16 && TARGET_AVX512VL"
{
operands[0] = lowpart_subreg (V8HFmode, operands[0], V2HFmode);
emit_insn (gen_avx512fp16_float<floatunssuffix>v2div2hf2 (operands[0],
operands[1]));
DONE;
})
(define_expand "avx512fp16_float<floatunssuffix>v2div2hf2"
[(set (match_operand:V8HF 0 "register_operand")
(vec_concat:V8HF
(any_float:V2HF (match_operand:V2DI 1 "vector_operand" "vm"))
(match_dup 2)))]
(any_float:V2HF (match_operand:V2DI 1 "vector_operand"))
(match_dup 2)))]
"TARGET_AVX512FP16 && TARGET_AVX512VL"
"operands[2] = CONST0_RTX (V6HFmode);")

@ -0,0 +1,61 @@
/* { dg-do compile } */
/* { dg-options "-O2 -mavx512fp16 -mavx512vl -ftree-slp-vectorize -mprefer-vector-width=512" } */
extern long long di[8];
extern unsigned long long udi[8];
extern int si[16];
extern unsigned int usi[16];
extern short hi[32];
extern unsigned short uhi[32];
extern _Float16 hf[32];
#define DO_PRAGMA(X) _Pragma(#X)
#define FLOATHFVV(size, mode) \
void __attribute__ ((noinline, noclone)) \
float##v##size##mode##v##size##hf () \
{\
int i; \
DO_PRAGMA (GCC unroll size) \
for (i = 0; i < size; i++) \
hf[i] = (_Float16) mode[i]; \
}
FLOATHFVV(32, hi)
FLOATHFVV(16, hi)
FLOATHFVV(8, hi)
FLOATHFVV(16, si)
FLOATHFVV(8, si)
FLOATHFVV(4, si)
FLOATHFVV(8, di)
FLOATHFVV(4, di)
FLOATHFVV(2, di)
FLOATHFVV(32, uhi)
FLOATHFVV(16, uhi)
FLOATHFVV(8, uhi)
FLOATHFVV(16, usi)
FLOATHFVV(8, usi)
FLOATHFVV(4, usi)
FLOATHFVV(8, udi)
FLOATHFVV(4, udi)
FLOATHFVV(2, udi)
/* { dg-final { scan-assembler-times "vcvtqq2phz\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtuqq2phz\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtqq2phy\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */
/* { dg-final { scan-assembler-times "vcvtuqq2phy\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */
/* { dg-final { scan-assembler-times "vcvtqq2phx\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */
/* { dg-final { scan-assembler-times "vcvtuqq2phx\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */
/* { dg-final { scan-assembler-times "vcvtdq2ph\[ \\t\]+\[^\{\n\]*\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtudq2ph\[ \\t\]+\[^\{\n\]*\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtdq2phy\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtudq2phy\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtdq2phx\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */
/* { dg-final { scan-assembler-times "vcvtudq2phx\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */
/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\[^\{\n\]*\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\[^\{\n\]*\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\[^\{\n\]*\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\[^\{\n\]*\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */