alpha.c (REG_RA, [...]): Fix merge problems.
* alpha.c (REG_RA, alpha_return_addr, output_epilog): Fix merge problems. * alpha.c (override_options): Don't know about scheduling for EV6. * alpha.md (ev5 function units): Don't overload as ev6. * alpha.c (alpha_adjust_cost): Simplify. Fix typo in ev5 mult case. * alpha.md (define_attr type): Add mvi. (ev5_e0): Define sceduling parameters for it. (TARGET_MAX insns): Type is mvi not shift. From-SVN: r17020
This commit is contained in:
Richard Henderson
Richard Henderson
parent
7120f213ca
commit
2625008199
@ -1,3 +1,16 @@
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Mon Dec 8 21:03:28 1997 Richard Henderson <rth@cygnus.com>
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* alpha.c (REG_RA, alpha_return_addr, output_epilog):
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Fix merge problems.
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* alpha.c (override_options): Don't know about scheduling for EV6.
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* alpha.md (ev5 function units): Don't overload as ev6.
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* alpha.c (alpha_adjust_cost): Simplify. Fix typo in ev5 mult case.
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* alpha.md (define_attr type): Add mvi.
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(ev5_e0): Define sceduling parameters for it.
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(TARGET_MAX insns): Type is mvi not shift.
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Mon Dec 8 18:15:00 1997 Richard Henderson <rth@cygnus.com>
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* alpha/win-nt.h (TRAMPOLINE_TEMPLATE): Fix backported gcc-2.8 bug.
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@ -106,14 +106,23 @@ static void alpha_sa_mask PROTO((unsigned long *imaskP,
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#else
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#define NUM_ARGS current_function_args_info
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#endif
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#if OPEN_VMS
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#define REG_PV 27
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#define REG_RA 26
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#else
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#define REG_RA 26
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#endif
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/* Parse target option strings. */
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void
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override_options ()
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{
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/* 971208 -- EV6 scheduling parameters are still secret, so don't even
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pretend and just schedule for an EV5 for now. -- r~ */
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alpha_cpu
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= TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
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= TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV5
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: (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
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if (alpha_cpu_string)
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@ -138,7 +147,8 @@ override_options ()
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target_flags &= ~ (MASK_CIX | MASK_MAX);
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}
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else if (! strcmp (alpha_cpu_string, "pca56")
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|| ! strcmp (alpha_cpu_string, "21164PC"))
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|| ! strcmp (alpha_cpu_string, "21164PC")
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|| ! strcmp (alpha_cpu_string, "21164pc"))
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{
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alpha_cpu = PROCESSOR_EV5;
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target_flags |= MASK_BWX | MASK_MAX;
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@ -147,7 +157,7 @@ override_options ()
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else if (! strcmp (alpha_cpu_string, "ev6")
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|| ! strcmp (alpha_cpu_string, "21264"))
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{
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alpha_cpu = PROCESSOR_EV6;
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alpha_cpu = PROCESSOR_EV5;
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target_flags |= MASK_BWX | MASK_CIX | MASK_MAX;
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}
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else
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@ -1191,6 +1201,7 @@ alpha_adjust_cost (insn, link, dep_insn, cost)
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int cost;
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{
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rtx set, set_src;
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enum attr_type insn_type, dep_insn_type;
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/* If the dependence is an anti-dependence, there is no cost. For an
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output dependence, there is sometimes a cost, but it doesn't seem
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@ -1199,17 +1210,22 @@ alpha_adjust_cost (insn, link, dep_insn, cost)
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if (REG_NOTE_KIND (link) != 0)
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return 0;
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/* If we can't recognize the insns, we can't really do anything. */
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if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
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return cost;
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insn_type = get_attr_type (insn);
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dep_insn_type = get_attr_type (dep_insn);
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if (alpha_cpu == PROCESSOR_EV5)
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{
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/* And the lord DEC saith: "A special bypass provides an effective
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latency of 0 cycles for an ICMP or ILOG insn producing the test
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operand of an IBR or CMOV insn." */
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if (recog_memoized (dep_insn) >= 0
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&& (get_attr_type (dep_insn) == TYPE_ICMP
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|| get_attr_type (dep_insn) == TYPE_ILOG)
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&& recog_memoized (insn) >= 0
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&& (get_attr_type (insn) == TYPE_IBR
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|| (get_attr_type (insn) == TYPE_CMOV
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if ((dep_insn_type == TYPE_ICMP
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|| dep_insn_type == TYPE_ILOG)
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&& (insn_type == TYPE_IBR
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|| (insn_type == TYPE_CMOV
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&& !((set = single_set (dep_insn)) != 0
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&& GET_CODE (PATTERN (insn)) == SET
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&& (set_src = SET_SRC (PATTERN (insn)),
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@ -1219,14 +1235,15 @@ alpha_adjust_cost (insn, link, dep_insn, cost)
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|| rtx_equal_p (set, XEXP (set_src, 2)))))))
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return 0;
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/* On EV5 it takes longer to get data to the multiplier than to
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anywhere else, so increase costs. */
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/* "The multiplier is unable to receive data from IEU bypass paths.
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The instruction issues at the expected time, but its latency is
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increased by the time it takes for the input data to become
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available to the multiplier" -- which happens in pipeline stage
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six, when results are comitted to the register file. */
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if (recog_memoized (insn) >= 0
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&& recog_memoized (dep_insn) >= 0
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&& (get_attr_type (insn) == TYPE_IMULL
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|| get_attr_type (insn) == TYPE_IMULQ
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|| get_attr_type (insn) == TYPE_IMULH)
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if ((insn_type == TYPE_IMULL
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|| insn_type == TYPE_IMULQ
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|| insn_type == TYPE_IMULH)
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&& (set = single_set (dep_insn)) != 0
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&& GET_CODE (PATTERN (insn)) == SET
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&& (set_src = SET_SRC (PATTERN (insn)),
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@ -1235,19 +1252,19 @@ alpha_adjust_cost (insn, link, dep_insn, cost)
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rtx_equal_p (set, XEXP (set_src, 0))
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|| rtx_equal_p (set, XEXP (set_src, 1))))
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{
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switch (get_attr_type (insn))
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switch (dep_insn_type)
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{
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/* These insns produce their results in pipeline stage five. */
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case TYPE_LD:
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case TYPE_CMOV:
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case TYPE_IMULL:
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case TYPE_IMULQ:
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case TYPE_IMULH:
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case TYPE_MVI:
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return cost + 1;
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case TYPE_JSR:
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case TYPE_IADD:
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case TYPE_ILOG:
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case TYPE_SHIFT:
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case TYPE_ICMP:
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/* Other integer insns produce results in pipeline stage four. */
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default:
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return cost + 2;
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}
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}
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@ -1257,12 +1274,12 @@ alpha_adjust_cost (insn, link, dep_insn, cost)
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/* On EV4, if INSN is a store insn and DEP_INSN is setting the data
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being stored, we can sometimes lower the cost. */
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if (recog_memoized (insn) >= 0 && get_attr_type (insn) == TYPE_ST
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if (insn_type == TYPE_ST
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&& (set = single_set (dep_insn)) != 0
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&& GET_CODE (PATTERN (insn)) == SET
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&& rtx_equal_p (SET_DEST (set), SET_SRC (PATTERN (insn))))
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{
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switch (get_attr_type (dep_insn))
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switch (dep_insn_type)
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{
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case TYPE_LD:
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/* No savings here. */
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@ -1285,11 +1302,9 @@ alpha_adjust_cost (insn, link, dep_insn, cost)
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two in the MD file. The only case that it is actually two is
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for the address in loads and stores. */
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if (recog_memoized (dep_insn) >= 0
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&& (get_attr_type (dep_insn) == TYPE_IADD
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|| get_attr_type (dep_insn) == TYPE_ILOG))
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if (dep_insn_type == TYPE_IADD || dep_insn_type == TYPE_ILOG)
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{
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switch (get_attr_type (insn))
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switch (insn_type)
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{
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case TYPE_LD:
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case TYPE_ST:
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@ -1302,10 +1317,7 @@ alpha_adjust_cost (insn, link, dep_insn, cost)
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/* The final case is when a compare feeds into an integer branch;
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the cost is only one cycle in that case. */
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if (recog_memoized (dep_insn) >= 0
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&& get_attr_type (dep_insn) == TYPE_ICMP
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&& recog_memoized (insn) >= 0
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&& get_attr_type (insn) == TYPE_IBR)
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if (dep_insn_type == TYPE_ICMP && insn_type == TYPE_IBR)
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return 1;
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}
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@ -1781,39 +1793,6 @@ alpha_builtin_saveregs (arglist)
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}
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}
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#if OPEN_VMS
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#define REG_PV 27
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#define REG_RA 26
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#else
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#define REG_RA 26
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#endif
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/* Find the current function's return address.
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??? It would be better to arrange things such that if we would ordinarily
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have been a leaf function and we didn't spill the hard reg that we
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wouldn't have to save the register in the prolog. But it's not clear
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how to get the right information at the right time. */
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static rtx alpha_return_addr_rtx;
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rtx
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alpha_return_addr ()
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{
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rtx ret;
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if ((ret = alpha_return_addr_rtx) == NULL)
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{
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alpha_return_addr_rtx = ret = gen_reg_rtx (Pmode);
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emit_insn_after (gen_rtx (SET, VOIDmode, ret,
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gen_rtx (REG, Pmode, REG_RA)),
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get_insns ());
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}
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return ret;
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}
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/* This page contains routines that are used to determine what the function
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prologue and epilogue code will do and write them out. */
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@ -2725,8 +2704,6 @@ output_epilog (file, size)
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/* Show that we know this function if it is called again. */
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SYMBOL_REF_FLAG (XEXP (DECL_RTL (current_function_decl), 0)) = 1;
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alpha_return_addr_rtx = 0;
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}
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#endif /* !OPEN_VMS */
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@ -24,7 +24,7 @@
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;; Processor type -- this attribute must exactly match the processor_type
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;; enumeration in alpha.h.
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(define_attr "cpu" "ev4,ev5,ev6"
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(define_attr "cpu" "ev4,ev5"
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(const (symbol_ref "alpha_cpu")))
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;; Define an insn type attribute. This is used in function unit delay
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@ -33,7 +33,7 @@
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;; separately.
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(define_attr "type"
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"ld,st,ibr,fbr,jsr,iadd,ilog,shift,cmov,icmp,imull,imulq,imulh,fadd,fmul,fcpys,fdivs,fdivt,ldsym,misc"
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"ld,st,ibr,fbr,jsr,iadd,ilog,shift,cmov,icmp,imull,imulq,imulh,fadd,fmul,fcpys,fdivs,fdivt,ldsym,misc,mvi"
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(const_string "iadd"))
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;; The TRAP_TYPE attribute marks instructions that may generate traps
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@ -122,60 +122,66 @@
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;; those as well.
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(define_function_unit "ev5_ebox" 2 0
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(and (eq_attr "cpu" "ev5,ev6")
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(eq_attr "type" "iadd,ilog,icmp,st,shift,imull,imulq,imulh"))
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "iadd,ilog,icmp,st,shift,imull,imulq,imulh,mvi"))
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1 1)
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;; Memory takes at least 2 clocks, and load cannot dual issue with stores.
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(define_function_unit "ev5_ebox" 2 0
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(and (eq_attr "cpu" "ev5,ev6")
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "ld,ldsym"))
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2 1)
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(define_function_unit "ev5_e0" 1 0
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(and (eq_attr "cpu" "ev5,ev6")
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "ld,ldsym"))
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0 1
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[(eq_attr "type" "st")])
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;; Conditional moves always take 2 ticks.
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(define_function_unit "ev5_ebox" 2 0
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(and (eq_attr "cpu" "ev5,ev6")
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "cmov"))
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2 1)
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;; Stores, shifts, and multiplies can only issue to E0
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;; Stores, shifts, multiplies can only issue to E0
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(define_function_unit "ev5_e0" 1 0
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(and (eq_attr "cpu" "ev5,ev6")
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "st"))
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1 1)
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;; Motion video insns also issue only to E0, and take two ticks.
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(define_function_unit "ev5_e0" 1 0
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "mvi"))
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2 1)
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;; But shifts and multiplies don't conflict with loads.
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(define_function_unit "ev5_e0" 1 0
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(and (eq_attr "cpu" "ev5,ev6")
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(eq_attr "type" "shift,imull,imulq,imulh"))
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "shift,imull,imulq,imulh,mvi"))
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1 1
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[(eq_attr "type" "st,shift,imull,imulq,imulh")])
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[(eq_attr "type" "st,shift,imull,imulq,imulh,mvi")])
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;; Branches can only issue to E1
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(define_function_unit "ev5_e1" 1 0
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(and (eq_attr "cpu" "ev5,ev6")
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "ibr,jsr"))
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1 1)
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;; Multiplies also use the integer multiplier.
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(define_function_unit "ev5_imult" 1 0
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(and (eq_attr "cpu" "ev5,ev6")
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "imull"))
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8 4)
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(define_function_unit "ev5_imult" 1 0
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(and (eq_attr "cpu" "ev5,ev6")
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "imulq"))
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12 8)
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(define_function_unit "ev5_imult" 1 0
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(and (eq_attr "cpu" "ev5,ev6")
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "imulh"))
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14 8)
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@ -183,33 +189,33 @@
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;; on either so we have to play the game again.
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(define_function_unit "ev5_fpu" 2 0
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(and (eq_attr "cpu" "ev5,ev6")
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "fadd,fmul,fcpys,fbr,fdivs,fdivt"))
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4 1)
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;; Multiplies (resp. adds) also use the fmul (resp. fadd) units.
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(define_function_unit "ev5_fm" 1 0
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(and (eq_attr "cpu" "ev5,ev6")
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "fmul"))
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4 1)
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(define_function_unit "ev5_fa" 1 0
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(and (eq_attr "cpu" "ev5,ev6")
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "fadd"))
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4 1)
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(define_function_unit "ev5_fa" 1 0
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(and (eq_attr "cpu" "ev5,ev6")
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "fbr"))
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1 1)
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(define_function_unit "ev5_fa" 1 0
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(and (eq_attr "cpu" "ev5,ev6")
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "fdivs"))
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15 1)
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(define_function_unit "ev5_fa" 1 0
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(and (eq_attr "cpu" "ev5,ev6")
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "fdivt"))
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22 1)
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@ -2069,7 +2075,7 @@
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(match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
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"TARGET_MAX"
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"minsb8 %r1,%2,%0"
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[(set_attr "type" "shift")])
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[(set_attr "type" "mvi")])
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(define_insn "uminqi3"
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[(set (match_operand:QI 0 "register_operand" "=r")
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@ -2077,7 +2083,7 @@
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(match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
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"TARGET_MAX"
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"minub8 %r1,%2,%0"
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[(set_attr "type" "shift")])
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[(set_attr "type" "mvi")])
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(define_insn "smaxqi3"
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[(set (match_operand:QI 0 "register_operand" "=r")
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@ -2085,7 +2091,7 @@
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(match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
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"TARGET_MAX"
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"maxsb8 %r1,%2,%0"
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[(set_attr "type" "shift")])
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[(set_attr "type" "mvi")])
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(define_insn "umaxqi3"
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[(set (match_operand:QI 0 "register_operand" "=r")
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@ -2093,7 +2099,7 @@
|
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(match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
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"TARGET_MAX"
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"maxub8 %r1,%2,%0"
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[(set_attr "type" "shift")])
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[(set_attr "type" "mvi")])
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(define_insn "sminhi3"
|
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[(set (match_operand:HI 0 "register_operand" "=r")
|
||||
@ -2101,7 +2107,7 @@
|
||||
(match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
|
||||
"TARGET_MAX"
|
||||
"minsw4 %r1,%2,%0"
|
||||
[(set_attr "type" "shift")])
|
||||
[(set_attr "type" "mvi")])
|
||||
|
||||
(define_insn "uminhi3"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r")
|
||||
@ -2109,7 +2115,7 @@
|
||||
(match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
|
||||
"TARGET_MAX"
|
||||
"minuw4 %r1,%2,%0"
|
||||
[(set_attr "type" "shift")])
|
||||
[(set_attr "type" "mvi")])
|
||||
|
||||
(define_insn "smaxhi3"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r")
|
||||
@ -2117,7 +2123,7 @@
|
||||
(match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
|
||||
"TARGET_MAX"
|
||||
"maxsw4 %r1,%2,%0"
|
||||
[(set_attr "type" "shift")])
|
||||
[(set_attr "type" "mvi")])
|
||||
|
||||
(define_insn "umaxhi3"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user