AVX-512. 61/n. Update FP logic insn patterns.
gcc/ * config/i386/sse.md (define_insn "<sse>_andnot<VF_128_256:mode>3<mask_name>"): Add masking, use VF_128_256 mode iterator and update assembler emit code. (define_insn "<sse>_andnot<VF_512:mode>3<mask_name>"): New. (define_expand "<any_logic:code><VF_128_256:mode>3<mask_name>"): Add masking, use VF_128_256 mode iterator. (define_expand "<any_logic:code><VF_512:mode>3<mask_name>"): New. (define_insn "*<any_logic:code><VF_128_256:mode>3<mask_name>"): Add masking, use VF_128_256 mode iterator and update assembler emit code. (define_insn "*<any_logic:code><VF_512:mode>3<mask_name>"): New. (define_mode_attr avx512flogicsuff): Delete. (define_insn "avx512f_<logic><mode>"): Ditto. (define_insn "*andnot<mode>3<mask_name>"): Update MODE_XI, MODE_OI, MODE_TI. (define_insn "<mask_codefor><code><mode>3<mask_name>"): Ditto. Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com> Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com> Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com> Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com> Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com> Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com> Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com> From-SVN: r216179
This commit is contained in:
Alexander Ivchenko
Kirill Yukhin
parent
06ba0585d6
commit
26358fb6a0
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@ -1,3 +1,29 @@
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2014-10-14 Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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Ilya Tocar <ilya.tocar@intel.com>
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Andrey Turetskiy <andrey.turetskiy@intel.com>
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Ilya Verbin <ilya.verbin@intel.com>
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Kirill Yukhin <kirill.yukhin@intel.com>
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Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* config/i386/sse.md
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(define_insn "<sse>_andnot<VF_128_256:mode>3<mask_name>"): Add masking,
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use VF_128_256 mode iterator and update assembler emit code.
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(define_insn "<sse>_andnot<VF_512:mode>3<mask_name>"): New.
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(define_expand "<any_logic:code><VF_128_256:mode>3<mask_name>"):
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Add masking, use VF_128_256 mode iterator.
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(define_expand "<any_logic:code><VF_512:mode>3<mask_name>"): New.
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(define_insn "*<any_logic:code><VF_128_256:mode>3<mask_name>"):
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Add masking, use VF_128_256 mode iterator and update assembler emit
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code.
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(define_insn "*<any_logic:code><VF_512:mode>3<mask_name>"): New.
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(define_mode_attr avx512flogicsuff): Delete.
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(define_insn "avx512f_<logic><mode>"): Ditto.
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(define_insn "*andnot<mode>3<mask_name>"): Update MODE_XI, MODE_OI,
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MODE_TI.
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(define_insn "<mask_codefor><code><mode>3<mask_name>"): Ditto.
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2014-10-14 Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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@ -2692,15 +2692,15 @@
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_insn "<sse>_andnot<mode>3"
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[(set (match_operand:VF 0 "register_operand" "=x,v")
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(and:VF
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(not:VF
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(match_operand:VF 1 "register_operand" "0,v"))
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(match_operand:VF 2 "nonimmediate_operand" "xm,vm")))]
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"TARGET_SSE"
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(define_insn "<sse>_andnot<mode>3<mask_name>"
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[(set (match_operand:VF_128_256 0 "register_operand" "=x,v")
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(and:VF_128_256
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(not:VF_128_256
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(match_operand:VF_128_256 1 "register_operand" "0,v"))
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(match_operand:VF_128_256 2 "nonimmediate_operand" "xm,vm")))]
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"TARGET_SSE && <mask_avx512vl_condition>"
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{
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static char buf[32];
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static char buf[128];
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const char *ops;
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const char *suffix;
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@ -2720,17 +2720,17 @@
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ops = "andn%s\t{%%2, %%0|%%0, %%2}";
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break;
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case 1:
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ops = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
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ops = "vandn%s\t{%%2, %%1, %%0<mask_operand3_1>|%%0<mask_operand3_1>, %%1, %%2}";
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break;
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default:
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gcc_unreachable ();
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}
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/* There is no vandnp[sd]. Use vpandnq. */
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if (<MODE_SIZE> == 64)
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/* There is no vandnp[sd] in avx512f. Use vpandn[qd]. */
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if (<mask_applied> && !TARGET_AVX512DQ)
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{
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suffix = "q";
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ops = "vpandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
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suffix = GET_MODE_INNER (<MODE>mode) == DFmode ? "q" : "d";
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ops = "vpandn%s\t{%%2, %%1, %%0<mask_operand3_1>|%%0<mask_operand3_1>, %%1, %%2}";
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}
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snprintf (buf, sizeof (buf), ops, suffix);
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@ -2750,30 +2750,63 @@
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]
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(const_string "<MODE>")))])
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(define_expand "<code><mode>3"
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(define_insn "<sse>_andnot<mode>3<mask_name>"
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[(set (match_operand:VF_512 0 "register_operand" "=v")
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(and:VF_512
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(not:VF_512
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(match_operand:VF_512 1 "register_operand" "v"))
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(match_operand:VF_512 2 "nonimmediate_operand" "vm")))]
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"TARGET_AVX512F"
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{
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static char buf[128];
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const char *ops;
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const char *suffix;
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suffix = "<ssemodesuffix>";
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ops = "";
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/* There is no vandnp[sd] in avx512f. Use vpandn[qd]. */
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if (!TARGET_AVX512DQ)
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{
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suffix = GET_MODE_INNER (<MODE>mode) == DFmode ? "q" : "d";
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ops = "p";
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}
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snprintf (buf, sizeof (buf),
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"v%sandn%s\t{%%2, %%1, %%0<mask_operand3_1>|%%0<mask_operand3_1>, %%1, %%2}",
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ops, suffix);
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return buf;
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}
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[(set_attr "type" "sselog")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_expand "<code><mode>3<mask_name>"
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[(set (match_operand:VF_128_256 0 "register_operand")
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(any_logic:VF_128_256
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(match_operand:VF_128_256 1 "nonimmediate_operand")
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(match_operand:VF_128_256 2 "nonimmediate_operand")))]
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"TARGET_SSE"
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(any_logic:VF_128_256
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(match_operand:VF_128_256 1 "nonimmediate_operand")
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(match_operand:VF_128_256 2 "nonimmediate_operand")))]
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"TARGET_SSE && <mask_avx512vl_condition>"
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"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
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(define_expand "<code><mode>3"
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(define_expand "<code><mode>3<mask_name>"
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[(set (match_operand:VF_512 0 "register_operand")
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(fpint_logic:VF_512
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(any_logic:VF_512
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(match_operand:VF_512 1 "nonimmediate_operand")
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(match_operand:VF_512 2 "nonimmediate_operand")))]
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"TARGET_AVX512F"
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"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
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(define_insn "*<code><mode>3"
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[(set (match_operand:VF 0 "register_operand" "=x,v")
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(any_logic:VF
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(match_operand:VF 1 "nonimmediate_operand" "%0,v")
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(match_operand:VF 2 "nonimmediate_operand" "xm,vm")))]
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"TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
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(define_insn "*<code><mode>3<mask_name>"
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[(set (match_operand:VF_128_256 0 "register_operand" "=x,v")
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(any_logic:VF_128_256
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(match_operand:VF_128_256 1 "nonimmediate_operand" "%0,v")
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(match_operand:VF_128_256 2 "nonimmediate_operand" "xm,vm")))]
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"TARGET_SSE && <mask_avx512vl_condition>
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&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
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{
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static char buf[32];
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static char buf[128];
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const char *ops;
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const char *suffix;
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@ -2793,17 +2826,17 @@
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ops = "<logic>%s\t{%%2, %%0|%%0, %%2}";
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break;
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case 1:
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ops = "v<logic>%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
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ops = "v<logic>%s\t{%%2, %%1, %%0<mask_operand3_1>|%%0<mask_operand3_1>, %%1, %%2}";
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break;
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default:
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gcc_unreachable ();
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}
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/* There is no v<logic>p[sd]. Use vp<logic>q. */
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if (<MODE_SIZE> == 64)
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/* There is no v<logic>p[sd] in avx512f. Use vp<logic>[dq]. */
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if (<mask_applied> && !TARGET_AVX512DQ)
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{
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suffix = "q";
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ops = "vp<logic>%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
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suffix = GET_MODE_INNER (<MODE>mode) == DFmode ? "q" : "d";
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ops = "vp<logic>%s\t{%%2, %%1, %%0<mask_operand3_1>|%%0<mask_operand3_1>, %%1, %%2}";
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}
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snprintf (buf, sizeof (buf), ops, suffix);
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@ -2823,6 +2856,36 @@
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]
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(const_string "<MODE>")))])
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(define_insn "*<code><mode>3<mask_name>"
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[(set (match_operand:VF_512 0 "register_operand" "=v")
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(any_logic:VF_512
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(match_operand:VF_512 1 "nonimmediate_operand" "%v")
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(match_operand:VF_512 2 "nonimmediate_operand" "vm")))]
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"TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
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{
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static char buf[128];
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const char *ops;
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const char *suffix;
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suffix = "<ssemodesuffix>";
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ops = "";
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/* There is no v<logic>p[sd] in avx512f. Use vp<logic>[dq]. */
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if ((<MODE_SIZE> == 64 || <mask_applied>) && !TARGET_AVX512DQ)
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{
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suffix = GET_MODE_INNER (<MODE>mode) == DFmode ? "q" : "d";
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ops = "p";
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}
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snprintf (buf, sizeof (buf),
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"v%s<logic>%s\t{%%2, %%1, %%0<mask_operand3_1>|%%0<mask_operand3_1>, %%1, %%2}",
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ops, suffix);
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return buf;
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}
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[(set_attr "type" "sselog")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_expand "copysign<mode>3"
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[(set (match_dup 4)
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(and:VF
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@ -3032,23 +3095,6 @@
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]
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(const_string "TI")))])
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;; There are no floating point xor for V16SF and V8DF in avx512f
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;; but we need them for negation. Instead we use int versions of
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;; xor. Maybe there could be a better way to do that.
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(define_mode_attr avx512flogicsuff
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[(V16SF "d") (V8DF "q")])
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(define_insn "avx512f_<logic><mode>"
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[(set (match_operand:VF_512 0 "register_operand" "=v")
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(fpint_logic:VF_512
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(match_operand:VF_512 1 "register_operand" "v")
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(match_operand:VF_512 2 "nonimmediate_operand" "vm")))]
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"TARGET_AVX512F"
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"vp<logic><avx512flogicsuff>\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "sselog")
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(set_attr "prefix" "evex")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; FMA floating point multiply/accumulate instructions. These include
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@ -10539,16 +10585,31 @@
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{
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case MODE_XI:
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gcc_assert (TARGET_AVX512F);
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tmp = "pandn<ssemodesuffix>";
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break;
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case MODE_OI:
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gcc_assert (TARGET_AVX2);
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gcc_assert (TARGET_AVX2 || TARGET_AVX512VL);
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case MODE_TI:
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gcc_assert (TARGET_SSE2);
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tmp = "pandn";
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gcc_assert (TARGET_SSE2 || TARGET_AVX512VL);
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switch (<MODE>mode)
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{
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case V16SImode:
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case V8DImode:
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if (TARGET_AVX512F)
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{
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tmp = "pandn<ssemodesuffix>";
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break;
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}
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case V8SImode:
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case V4DImode:
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case V4SImode:
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case V2DImode:
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if (TARGET_AVX512VL)
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{
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tmp = "pandn<ssemodesuffix>";
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break;
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}
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default:
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tmp = TARGET_AVX512VL ? "pandnq" : "pandn";
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}
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break;
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case MODE_V16SF:
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@ -10633,16 +10694,31 @@
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{
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case MODE_XI:
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gcc_assert (TARGET_AVX512F);
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tmp = "p<logic><ssemodesuffix>";
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break;
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case MODE_OI:
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gcc_assert (TARGET_AVX2);
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gcc_assert (TARGET_AVX2 || TARGET_AVX512VL);
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case MODE_TI:
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gcc_assert (TARGET_SSE2);
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tmp = "p<logic>";
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gcc_assert (TARGET_SSE2 || TARGET_AVX512VL);
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switch (<MODE>mode)
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{
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case V16SImode:
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case V8DImode:
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if (TARGET_AVX512F)
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{
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tmp = "p<logic><ssemodesuffix>";
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break;
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}
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case V8SImode:
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case V4DImode:
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case V4SImode:
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case V2DImode:
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if (TARGET_AVX512VL)
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{
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tmp = "p<logic><ssemodesuffix>";
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break;
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}
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default:
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tmp = TARGET_AVX512VL ? "p<logic>q" : "p<logic>";
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}
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break;
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case MODE_V16SF:
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