[NDS32] Add load_multiple,store_multiple and new attribute combo.
gcc/ * config/nds32/nds32.md (type): Add load_multiple and store_multiple. (combo): New attribute. * config/nds32/nds32-multiple.md: Refine patterns with new attributes. Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com> From-SVN: r258232
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@ -1,3 +1,10 @@
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2018-03-04 Kito Cheng <kito.cheng@gmail.com>
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Chung-Ju Wu <jasonwucj@gmail.com>
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* config/nds32/nds32.md (type): Add load_multiple and store_multiple.
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(combo): New attribute.
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* config/nds32/nds32-multiple.md: Refine patterns with new attributes.
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2018-03-03 Chung-Ju Wu <jasonwucj@gmail.com>
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* config/nds32/nds32.opt: Change -mcmodel= default value.
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@ -96,8 +96,9 @@
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(mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
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"(XVECLEN (operands[0], 0) == 8)"
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"lmw.bi\t%2, [%1], %9, 0x0"
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[(set_attr "type" "load")
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(set_attr "length" "4")]
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[(set_attr "type" "load_multiple")
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(set_attr "combo" "8")
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(set_attr "length" "4")]
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)
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(define_insn "*lmwsi7"
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@ -118,8 +119,9 @@
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(mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
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"(XVECLEN (operands[0], 0) == 7)"
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"lmw.bi\t%2, [%1], %8, 0x0"
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[(set_attr "type" "load")
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(set_attr "length" "4")]
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[(set_attr "type" "load_multiple")
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(set_attr "combo" "7")
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(set_attr "length" "4")]
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)
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(define_insn "*lmwsi6"
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@ -138,8 +140,9 @@
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(mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
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"(XVECLEN (operands[0], 0) == 6)"
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"lmw.bi\t%2, [%1], %7, 0x0"
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[(set_attr "type" "load")
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(set_attr "length" "4")]
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[(set_attr "type" "load_multiple")
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(set_attr "combo" "6")
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(set_attr "length" "4")]
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)
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(define_insn "*lmwsi5"
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@ -156,8 +159,9 @@
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(mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
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"(XVECLEN (operands[0], 0) == 5)"
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"lmw.bi\t%2, [%1], %6, 0x0"
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[(set_attr "type" "load")
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(set_attr "length" "4")]
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[(set_attr "type" "load_multiple")
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(set_attr "combo" "5")
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(set_attr "length" "4")]
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)
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(define_insn "*lmwsi4"
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@ -172,8 +176,9 @@
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(mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
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"(XVECLEN (operands[0], 0) == 4)"
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"lmw.bi\t%2, [%1], %5, 0x0"
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[(set_attr "type" "load")
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(set_attr "length" "4")]
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[(set_attr "type" "load_multiple")
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(set_attr "combo" "4")
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(set_attr "length" "4")]
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)
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(define_insn "*lmwsi3"
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@ -186,8 +191,9 @@
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(mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
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"(XVECLEN (operands[0], 0) == 3)"
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"lmw.bi\t%2, [%1], %4, 0x0"
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[(set_attr "type" "load")
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(set_attr "length" "4")]
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[(set_attr "type" "load_multiple")
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(set_attr "combo" "3")
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(set_attr "length" "4")]
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)
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(define_insn "*lmwsi2"
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@ -198,8 +204,9 @@
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(mem:SI (plus:SI (match_dup 1) (const_int 4))))])]
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"(XVECLEN (operands[0], 0) == 2)"
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"lmw.bi\t%2, [%1], %3, 0x0"
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[(set_attr "type" "load")
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(set_attr "length" "4")]
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[(set_attr "type" "load_multiple")
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(set_attr "combo" "2")
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(set_attr "length" "4")]
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)
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@ -280,8 +287,9 @@
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(match_operand:SI 9 "register_operand" ""))])]
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"(XVECLEN (operands[0], 0) == 8)"
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"smw.bi\t%2, [%1], %9, 0x0"
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[(set_attr "type" "store")
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(set_attr "length" "4")]
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[(set_attr "type" "store_multiple")
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(set_attr "combo" "8")
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(set_attr "length" "4")]
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)
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(define_insn "*stmsi7"
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@ -302,8 +310,9 @@
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(match_operand:SI 8 "register_operand" ""))])]
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"(XVECLEN (operands[0], 0) == 7)"
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"smw.bi\t%2, [%1], %8, 0x0"
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[(set_attr "type" "store")
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(set_attr "length" "4")]
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[(set_attr "type" "store_multiple")
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(set_attr "combo" "7")
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(set_attr "length" "4")]
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)
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(define_insn "*stmsi6"
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@ -322,8 +331,9 @@
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(match_operand:SI 7 "register_operand" ""))])]
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"(XVECLEN (operands[0], 0) == 6)"
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"smw.bi\t%2, [%1], %7, 0x0"
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[(set_attr "type" "store")
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(set_attr "length" "4")]
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[(set_attr "type" "store_multiple")
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(set_attr "combo" "6")
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(set_attr "length" "4")]
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)
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(define_insn "*stmsi5"
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@ -340,8 +350,9 @@
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(match_operand:SI 6 "register_operand" ""))])]
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"(XVECLEN (operands[0], 0) == 5)"
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"smw.bi\t%2, [%1], %6, 0x0"
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[(set_attr "type" "store")
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(set_attr "length" "4")]
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[(set_attr "type" "store_multiple")
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(set_attr "combo" "5")
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(set_attr "length" "4")]
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)
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(define_insn "*stmsi4"
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@ -356,8 +367,9 @@
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(match_operand:SI 5 "register_operand" ""))])]
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"(XVECLEN (operands[0], 0) == 4)"
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"smw.bi\t%2, [%1], %5, 0x0"
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[(set_attr "type" "store")
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(set_attr "length" "4")]
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[(set_attr "type" "store_multiple")
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(set_attr "combo" "4")
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(set_attr "length" "4")]
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)
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(define_insn "*stmsi3"
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@ -370,8 +382,9 @@
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(match_operand:SI 4 "register_operand" ""))])]
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"(XVECLEN (operands[0], 0) == 3)"
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"smw.bi\t%2, [%1], %4, 0x0"
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[(set_attr "type" "store")
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(set_attr "length" "4")]
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[(set_attr "type" "store_multiple")
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(set_attr "combo" "3")
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(set_attr "length" "4")]
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)
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(define_insn "*stmsi2"
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@ -382,8 +395,9 @@
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(match_operand:SI 3 "register_operand" ""))])]
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"(XVECLEN (operands[0], 0) == 2)"
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"smw.bi\t%2, [%1], %3, 0x0"
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[(set_attr "type" "store")
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(set_attr "length" "4")]
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[(set_attr "type" "store_multiple")
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(set_attr "combo" "2")
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(set_attr "length" "4")]
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)
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;; Move a block of memory if it is word aligned and MORE than 2 words long.
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@ -52,13 +52,17 @@
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;; Insn type, it is used to default other attribute values.
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(define_attr "type"
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"unknown,move,load,store,alu,compare,branch,call,misc"
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"unknown,move,load,store,load_multiple,store_multiple,alu,compare,branch,call,misc"
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(const_string "unknown"))
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;; Length, in bytes, default is 4-bytes.
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(define_attr "length" "" (const_int 4))
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;; Indicate the amount of micro instructions.
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(define_attr "combo"
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"0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25"
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(const_string "1"))
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;; Enabled, which is used to enable/disable insn alternatives.
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;; Note that we use length and TARGET_16_BIT here as criteria.
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@ -2166,7 +2170,8 @@ create_template:
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{
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return nds32_output_stack_push (operands[0]);
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}
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[(set_attr "type" "misc")
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[(set_attr "type" "store_multiple")
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(set_attr "combo" "12")
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(set_attr "enabled" "1")
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(set (attr "length")
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(if_then_else (match_test "TARGET_V3PUSH
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@ -2188,7 +2193,8 @@ create_template:
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{
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return nds32_output_stack_pop (operands[0]);
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}
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[(set_attr "type" "misc")
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[(set_attr "type" "load_multiple")
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(set_attr "combo" "12")
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(set_attr "enabled" "1")
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(set (attr "length")
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(if_then_else (match_test "TARGET_V3PUSH
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