OpenE2K/gcc
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

PR target/6512, PR target/5628

Browse Source 
PR target/6512, PR target/5628
	* config/sparc/sparc.md (movdf_insn_v9only_novis): Don't allow >= %f32
	when memory is not aligned.
	(movdf_insn_v9only_vis): Likewise.
	* config/sparc/sparc.h (SECONDARY_INPUT_RELOAD_CLASS): Request a FP_REGS
	temporary for EXTRA_FP_REGS DFmode load from unaligned memory.
	(SECONDARY_OUTPUT_RELOAD_CLASS): Similarly.

From-SVN: r52995
This commit is contained in:
Jakub Jelinek 2002-05-01 10:27:55 +02:00 committed by Jakub Jelinek
parent 2600218b4d
commit 26aeede496
3 changed files with 42 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
gcc/ChangeLog
View File

@ -1,3 +1,13 @@
2002-05-01 Jakub Jelinek <jakub@redhat.com>
PR target/6512, PR target/5628
* config/sparc/sparc.md (movdf_insn_v9only_novis): Don't allow >= %f32
when memory is not aligned.
(movdf_insn_v9only_vis): Likewise.
* config/sparc/sparc.h (SECONDARY_INPUT_RELOAD_CLASS): Request a FP_REGS
temporary for EXTRA_FP_REGS DFmode load from unaligned memory.
(SECONDARY_OUTPUT_RELOAD_CLASS): Similarly.
2002-05-01 Aldy Hernandez <aldyh@redhat.com>
* gcc.dg/altivec-7.c: New.

45
gcc/config/sparc/sparc.h
View File

@ -1423,7 +1423,10 @@ extern const char leaf_reg_remap[];
We need a temporary when loading/storing a HImode/QImode value
between memory and the FPU registers. This can happen when combine puts
a paradoxical subreg in a float/fix conversion insn. */
a paradoxical subreg in a float/fix conversion insn.
We need a temporary when loading/storing a DFmode value between
unaligned memory and the upper FPU registers. */
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
((FP_REG_CLASS_P (CLASS) \
@ -1432,28 +1435,36 @@ extern const char leaf_reg_remap[];
|| ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
&& true_regnum (IN) == -1))) \
? GENERAL_REGS \
: (((TARGET_CM_MEDANY \
&& symbolic_operand ((IN), (MODE))) \
|| (TARGET_CM_EMBMEDANY \
&& text_segment_operand ((IN), (MODE)))) \
&& !flag_pic) \
? GENERAL_REGS \
: NO_REGS)
: ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
&& GET_CODE (IN) == MEM && TARGET_ARCH32 \
&& ! mem_min_alignment ((IN), 8)) \
? FP_REGS \
: (((TARGET_CM_MEDANY \
&& symbolic_operand ((IN), (MODE))) \
|| (TARGET_CM_EMBMEDANY \
&& text_segment_operand ((IN), (MODE)))) \
&& !flag_pic) \
? GENERAL_REGS \
: NO_REGS)
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
((FP_REG_CLASS_P (CLASS) \
((FP_REG_CLASS_P (CLASS) \
&& ((MODE) == HImode || (MODE) == QImode) \
&& (GET_CODE (IN) == MEM \
|| ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
&& true_regnum (IN) == -1))) \
? GENERAL_REGS \
: (((TARGET_CM_MEDANY \
&& symbolic_operand ((IN), (MODE))) \
|| (TARGET_CM_EMBMEDANY \
&& text_segment_operand ((IN), (MODE)))) \
&& !flag_pic) \
? GENERAL_REGS \
: NO_REGS)
? GENERAL_REGS \
: ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
&& GET_CODE (IN) == MEM && TARGET_ARCH32 \
&& ! mem_min_alignment ((IN), 8)) \
? FP_REGS \
: (((TARGET_CM_MEDANY \
&& symbolic_operand ((IN), (MODE))) \
|| (TARGET_CM_EMBMEDANY \
&& text_segment_operand ((IN), (MODE)))) \
&& !flag_pic) \
? GENERAL_REGS \
: NO_REGS)
/* On SPARC it is not possible to directly move data between
GENERAL_REGS and FP_REGS. */

8
gcc/config/sparc/sparc.md
View File

@ -3535,8 +3535,8 @@
;; We have available v9 double floats but not 64-bit
;; integer registers and no VIS.
(define_insn "*movdf_insn_v9only_novis"
[(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,T,W,U,T,e,*r,o")
(match_operand:DF 1 "input_operand" "e,W#F,G,e,T,U,o#F,*roF,*rGe"))]
[(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,T,W,U,T,f,*r,o")
(match_operand:DF 1 "input_operand" "e,W#F,G,e,T,U,o#F,*roF,*rGf"))]
"TARGET_FPU
&& TARGET_V9
&& ! TARGET_VIS
@ -3561,8 +3561,8 @@
;; We have available v9 double floats but not 64-bit
;; integer registers but we have VIS.
(define_insn "*movdf_insn_v9only_vis"
[(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,T,W,U,T,e,*r,o")
(match_operand:DF 1 "input_operand" "G,e,W#F,G,e,T,U,o#F,*roGF,*rGe"))]
[(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,T,W,U,T,f,*r,o")
(match_operand:DF 1 "input_operand" "G,e,W#F,G,e,T,U,o#F,*roGF,*rGf"))]
"TARGET_FPU
&& TARGET_VIS
&& ! TARGET_ARCH64