From 26e2f443df7e81d1adc3ed509928ddc06df432bd Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Fri, 7 Oct 2011 10:23:47 -0700 Subject: [PATCH] Fix VIS3 assembler check and conditionalize testsuite on VIS3 support. gcc/ PR 50655 * configure.ac: Add .register directives to VIS3 test. * configure: Regenerate. gcc/testsuite/ PR 50655 * gcc.target/sparc/sparc.exp: Add vis3 target test. * gcc.target/sparc/cmask.c: Use it. * gcc.target/sparc/fhalve.c: Likewise. * gcc.target/sparc/fnegop.c: Likewise. * gcc.target/sparc/fpadds.c: Likewise. * gcc.target/sparc/fshift.c: Likewise. * gcc.target/sparc/fucmp.c: Likewise. * gcc.target/sparc/lzd.c: Likewise. * gcc.target/sparc/vis3misc.c: Likewise. * gcc.target/sparc/xmul.c: Likewise. From-SVN: r179667 --- gcc/ChangeLog | 6 ++++++ gcc/configure | 2 ++ gcc/configure.ac | 2 ++ gcc/testsuite/ChangeLog | 16 +++++++++++++++- gcc/testsuite/gcc.target/sparc/cmask.c | 2 +- gcc/testsuite/gcc.target/sparc/fhalve.c | 2 +- gcc/testsuite/gcc.target/sparc/fnegop.c | 2 +- gcc/testsuite/gcc.target/sparc/fpadds.c | 2 +- gcc/testsuite/gcc.target/sparc/fshift.c | 2 +- gcc/testsuite/gcc.target/sparc/fucmp.c | 2 +- gcc/testsuite/gcc.target/sparc/lzd.c | 2 +- gcc/testsuite/gcc.target/sparc/sparc.exp | 11 +++++++++++ gcc/testsuite/gcc.target/sparc/vis3misc.c | 2 +- gcc/testsuite/gcc.target/sparc/xmul.c | 2 +- 14 files changed, 45 insertions(+), 10 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f840e4678ca..573ce6ec279 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2011-10-07 David S. Miller + + PR 50655 + * configure.ac: Add .register directives to VIS3 test. + * configure: Regenerate. + 2011-10-07 Richard Henderson * config.gcc (x86_64-*): Add core-avx-i, core-avx2 for with_cpu. diff --git a/gcc/configure b/gcc/configure index ac327053bc9..cb55ddaa2a4 100755 --- a/gcc/configure +++ b/gcc/configure @@ -24060,6 +24060,8 @@ else gcc_cv_as_sparc_fmaf=no if test x$gcc_cv_as != x; then $as_echo '.text + .register %g2, #scratch + .register %g3, #scratch .align 4 fmaddd %f0, %f2, %f4, %f6 addxccc %g1, %g2, %g3 diff --git a/gcc/configure.ac b/gcc/configure.ac index ed52c918afa..a7b94e64451 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -3491,6 +3491,8 @@ foo: gcc_cv_as_sparc_fmaf,, [-xarch=v9d], [.text + .register %g2, #scratch + .register %g3, #scratch .align 4 fmaddd %f0, %f2, %f4, %f6 addxccc %g1, %g2, %g3 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index aff35a60701..ea79b6075fb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,17 @@ +2011-10-07 David S. Miller + + PR 50655 + * gcc.target/sparc/sparc.exp: Add vis3 target test. + * gcc.target/sparc/cmask.c: Use it. + * gcc.target/sparc/fhalve.c: Likewise. + * gcc.target/sparc/fnegop.c: Likewise. + * gcc.target/sparc/fpadds.c: Likewise. + * gcc.target/sparc/fshift.c: Likewise. + * gcc.target/sparc/fucmp.c: Likewise. + * gcc.target/sparc/lzd.c: Likewise. + * gcc.target/sparc/vis3misc.c: Likewise. + * gcc.target/sparc/xmul.c: Likewise. + 2011-10-07 Richard Henderson * gcc.target/i386/avx256-unaligned-load-2.c: Tweek vinsert pattern @@ -17,7 +31,7 @@ 2011-10-06 Joern Rennecke * gcc.dg/pr47276.c (ASMNAME, ASMNAME2, STRING): Define. - (__EI___vsyslog_chk, __EI_syslog, __EI_vsyslog): Use ASMNAME. + (__EI___vsyslog_chk, __EI_syslog, __EI_vsyslog): Use ASMNAME. (syslog, vsyslog, __vsyslog_chk): Likewise. * gcc.dg/lto/20081222_1.c (ASMNAME, ASMNAME2, STRING): Define. diff --git a/gcc/testsuite/gcc.target/sparc/cmask.c b/gcc/testsuite/gcc.target/sparc/cmask.c index b3168ec321d..989274c6858 100644 --- a/gcc/testsuite/gcc.target/sparc/cmask.c +++ b/gcc/testsuite/gcc.target/sparc/cmask.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { vis3 } } } */ /* { dg-options "-mcpu=niagara3 -mvis" } */ void test_cm8 (long x) diff --git a/gcc/testsuite/gcc.target/sparc/fhalve.c b/gcc/testsuite/gcc.target/sparc/fhalve.c index 340b936b8fa..737fc71bbcf 100644 --- a/gcc/testsuite/gcc.target/sparc/fhalve.c +++ b/gcc/testsuite/gcc.target/sparc/fhalve.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { vis3 } } } */ /* { dg-options "-mcpu=niagara3 -mvis" } */ float test_fhadds (float x, float y) diff --git a/gcc/testsuite/gcc.target/sparc/fnegop.c b/gcc/testsuite/gcc.target/sparc/fnegop.c index 25f8c199e24..3e3e72c820c 100644 --- a/gcc/testsuite/gcc.target/sparc/fnegop.c +++ b/gcc/testsuite/gcc.target/sparc/fnegop.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { vis3 } } } */ /* { dg-options "-O2 -mcpu=niagara3 -mvis" } */ float test_fnadds(float x, float y) diff --git a/gcc/testsuite/gcc.target/sparc/fpadds.c b/gcc/testsuite/gcc.target/sparc/fpadds.c index d0704e03eda..f55cb057a2a 100644 --- a/gcc/testsuite/gcc.target/sparc/fpadds.c +++ b/gcc/testsuite/gcc.target/sparc/fpadds.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { vis3 } } } */ /* { dg-options "-mcpu=niagara3 -mvis" } */ typedef int __v2si __attribute__((vector_size(8))); typedef int __v1si __attribute__((vector_size(4))); diff --git a/gcc/testsuite/gcc.target/sparc/fshift.c b/gcc/testsuite/gcc.target/sparc/fshift.c index a12df0451cb..6adbed69171 100644 --- a/gcc/testsuite/gcc.target/sparc/fshift.c +++ b/gcc/testsuite/gcc.target/sparc/fshift.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { vis3 } } } */ /* { dg-options "-mcpu=niagara3 -mvis" } */ typedef int __v2si __attribute__((vector_size(8))); typedef short __v4hi __attribute__((vector_size(8))); diff --git a/gcc/testsuite/gcc.target/sparc/fucmp.c b/gcc/testsuite/gcc.target/sparc/fucmp.c index 7f291c3e7ed..4e7ecadcd4a 100644 --- a/gcc/testsuite/gcc.target/sparc/fucmp.c +++ b/gcc/testsuite/gcc.target/sparc/fucmp.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { vis3 } } } */ /* { dg-options "-mcpu=niagara3 -mvis" } */ typedef unsigned char vec8 __attribute__((vector_size(8))); diff --git a/gcc/testsuite/gcc.target/sparc/lzd.c b/gcc/testsuite/gcc.target/sparc/lzd.c index a8978296300..5ffaf56e558 100644 --- a/gcc/testsuite/gcc.target/sparc/lzd.c +++ b/gcc/testsuite/gcc.target/sparc/lzd.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { vis3 } } } */ /* { dg-options "-mcpu=niagara3" } */ int test_clz(int a) { diff --git a/gcc/testsuite/gcc.target/sparc/sparc.exp b/gcc/testsuite/gcc.target/sparc/sparc.exp index 9658d08bc9c..51c9c16ecb7 100644 --- a/gcc/testsuite/gcc.target/sparc/sparc.exp +++ b/gcc/testsuite/gcc.target/sparc/sparc.exp @@ -24,6 +24,17 @@ if ![istarget sparc*-*-*] then { # Load support procs. load_lib gcc-dg.exp +# Return 1 if vis3 instructions can be compiled. +proc check_effective_target_vis3 { } { + return [check_no_compiler_messages vis3 object { + long long + _vis3_fpadd64 (long long __X, long long __Y) + { + return __builtin_vis_fpadd64 (__X, __Y); + } + } "-mcpu=niagara3 -mvis" ] +} + # If a testcase doesn't have special options, use these. global DEFAULT_CFLAGS if ![info exists DEFAULT_CFLAGS] then { diff --git a/gcc/testsuite/gcc.target/sparc/vis3misc.c b/gcc/testsuite/gcc.target/sparc/vis3misc.c index 8a9535e8fb5..e3ef49e210d 100644 --- a/gcc/testsuite/gcc.target/sparc/vis3misc.c +++ b/gcc/testsuite/gcc.target/sparc/vis3misc.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { vis3 } } } */ /* { dg-options "-mcpu=niagara3 -mvis" } */ typedef int __v2si __attribute__((vector_size(8))); typedef short __v4hi __attribute__((vector_size(8))); diff --git a/gcc/testsuite/gcc.target/sparc/xmul.c b/gcc/testsuite/gcc.target/sparc/xmul.c index ce80e6cbbe0..5d249d092db 100644 --- a/gcc/testsuite/gcc.target/sparc/xmul.c +++ b/gcc/testsuite/gcc.target/sparc/xmul.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { vis3 } } } */ /* { dg-options "-mcpu=niagara3 -mvis" } */ typedef long long int64_t;