mn10300.h (FIRST_PSEUDO_REGISTER): Increment by one.
* config/mn10300/mn10300.h (FIRST_PSEUDO_REGISTER): Increment by
one.
(MDR_REGNUM): Define.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Add MDR as a fixed
register.
(REG_CLASS_CONTENTS): Add MDR to ALL_REGS.
(INCOMING_RETURN_ADDR_RTX): Define in terms of MDR.
(REGISTER_NAMES): Add MDR.
(DWARF2_DEBUGGING_INFO): Define to 1.
* config/mn10300/mn10300.c (TARGET_EXCEPT_UNWIND_INFO): Define.
(F): New function. Sets RTX_FRAME_RELATED_P.
(mn10300_gen_multiple_store): Use F.
(expand_prologue): Use F. Use gen_movsf() to push floating
point registers.
(expand_epilogue): Use gen_movsf() to pop floating point
registers.
(mn10300_option_override): Disable combine stack adjust pass.
From-SVN: r165015
This commit is contained in:
Nick Clifton
Nick Clifton
parent
28ce2f29b8
commit
2720cc4717
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@ -1,3 +1,23 @@
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2010-10-06 Nick Clifton <nickc@redhat.com>
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* config/mn10300/mn10300.h (FIRST_PSEUDO_REGISTER): Increment by
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one.
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(MDR_REGNUM): Define.
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(FIXED_REGISTERS, CALL_USED_REGISTERS): Add MDR as a fixed
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register.
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(REG_CLASS_CONTENTS): Add MDR to ALL_REGS.
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(INCOMING_RETURN_ADDR_RTX): Define in terms of MDR.
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(REGISTER_NAMES): Add MDR.
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(DWARF2_DEBUGGING_INFO): Define to 1.
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* config/mn10300/mn10300.c (TARGET_EXCEPT_UNWIND_INFO): Define.
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(F): New function. Sets RTX_FRAME_RELATED_P.
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(mn10300_gen_multiple_store): Use F.
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(expand_prologue): Use F. Use gen_movsf() to push floating
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point registers.
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(expand_epilogue): Use gen_movsf() to pop floating point
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registers.
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(mn10300_option_override): Disable combine stack adjust pass.
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2010-10-06 Thomas Schwinge <thomas@schwinge.name>
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PR target/45901
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@ -93,6 +93,9 @@ static void mn10300_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_
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static bool mn10300_can_output_mi_thunk (const_tree, HOST_WIDE_INT, HOST_WIDE_INT, const_tree);
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/* Initialize the GCC target structure. */
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#undef TARGET_EXCEPT_UNWIND_INFO
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#define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
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#undef TARGET_ASM_ALIGNED_HI_OP
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#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
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@ -187,6 +190,12 @@ mn10300_option_override (void)
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{
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if (TARGET_AM33)
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target_flags &= ~MASK_MULT_BUG;
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/* FIXME: The combine stack adjustments pass is breaking
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cc0-setter/cc0-user relationship by inserting a jump
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instruction. This should be investigated, but for now
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just disable the pass. */
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flag_combine_stack_adjustments = 0;
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}
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static void
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@ -661,6 +670,13 @@ mn10300_get_live_callee_saved_regs (void)
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return mask;
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}
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static rtx
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F (rtx r)
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{
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RTX_FRAME_RELATED_P (r) = 1;
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return r;
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}
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/* Generate an instruction that pushes several registers onto the stack.
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Register K will be saved if bit K in MASK is set. The function does
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nothing if MASK is zero.
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@ -702,11 +718,11 @@ mn10300_gen_multiple_store (int mask)
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/* Create the instruction that updates the stack pointer. */
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XVECEXP (par, 0, 0)
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= gen_rtx_SET (SImode,
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stack_pointer_rtx,
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gen_rtx_PLUS (SImode,
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stack_pointer_rtx,
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GEN_INT (-count * 4)));
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= F (gen_rtx_SET (SImode,
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stack_pointer_rtx,
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gen_rtx_PLUS (SImode,
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stack_pointer_rtx,
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GEN_INT (-count * 4))));
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/* Create each store. */
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pari = 1;
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@ -717,14 +733,13 @@ mn10300_gen_multiple_store (int mask)
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stack_pointer_rtx,
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GEN_INT (-pari * 4));
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XVECEXP(par, 0, pari)
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= gen_rtx_SET (VOIDmode,
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gen_rtx_MEM (SImode, address),
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gen_rtx_REG (SImode, i));
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= F (gen_rtx_SET (VOIDmode,
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gen_rtx_MEM (SImode, address),
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gen_rtx_REG (SImode, i)));
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pari += 1;
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}
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par = emit_insn (par);
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RTX_FRAME_RELATED_P (par) = 1;
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F (emit_insn (par));
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}
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}
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@ -751,7 +766,6 @@ expand_prologue (void)
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save_a0_no_merge } strategy;
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unsigned int strategy_size = (unsigned)-1, this_strategy_size;
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rtx reg;
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rtx insn;
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/* We have several different strategies to save FP registers.
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We can store them using SP offsets, which is beneficial if
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@ -891,25 +905,25 @@ expand_prologue (void)
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{
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case save_sp_no_merge:
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case save_a0_no_merge:
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emit_insn (gen_addsi3 (stack_pointer_rtx,
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stack_pointer_rtx,
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GEN_INT (-4 * num_regs_to_save)));
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F (emit_insn (gen_addsi3 (stack_pointer_rtx,
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stack_pointer_rtx,
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GEN_INT (-4 * num_regs_to_save))));
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xsize = 0;
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break;
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case save_sp_partial_merge:
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emit_insn (gen_addsi3 (stack_pointer_rtx,
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stack_pointer_rtx,
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GEN_INT (-128)));
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F (emit_insn (gen_addsi3 (stack_pointer_rtx,
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stack_pointer_rtx,
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GEN_INT (-128))));
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xsize = 128 - 4 * num_regs_to_save;
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size -= xsize;
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break;
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case save_sp_merge:
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case save_a0_merge:
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emit_insn (gen_addsi3 (stack_pointer_rtx,
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stack_pointer_rtx,
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GEN_INT (-(size + 4 * num_regs_to_save))));
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F (emit_insn (gen_addsi3 (stack_pointer_rtx,
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stack_pointer_rtx,
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GEN_INT (-(size + 4 * num_regs_to_save)))));
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/* We'll have to adjust FP register saves according to the
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frame size. */
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xsize = size;
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@ -934,9 +948,9 @@ expand_prologue (void)
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case save_a0_merge:
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case save_a0_no_merge:
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reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM);
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emit_insn (gen_movsi (reg, stack_pointer_rtx));
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F (emit_insn (gen_movsi (reg, stack_pointer_rtx)));
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if (xsize)
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emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)));
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F (emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize))));
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reg = gen_rtx_POST_INC (SImode, reg);
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break;
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@ -967,22 +981,21 @@ expand_prologue (void)
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xsize += 4;
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}
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insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr),
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gen_rtx_REG (SImode, i)));
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RTX_FRAME_RELATED_P (insn) = 1;
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F (emit_insn (gen_movsf (gen_rtx_MEM (SFmode, addr),
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gen_rtx_REG (SFmode, i))));
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}
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}
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/* Now put the frame pointer into the frame pointer register. */
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if (frame_pointer_needed)
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emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
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F (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx));
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/* Allocate stack for this frame. */
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if (size)
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emit_insn (gen_addsi3 (stack_pointer_rtx,
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stack_pointer_rtx,
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GEN_INT (-size)));
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F (emit_insn (gen_addsi3 (stack_pointer_rtx,
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stack_pointer_rtx,
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GEN_INT (-size))));
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if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
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emit_insn (gen_GOTaddr2picreg ());
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}
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@ -1169,8 +1182,8 @@ expand_epilogue (void)
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size += 4;
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emit_insn (gen_movsi (gen_rtx_REG (SImode, i),
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gen_rtx_MEM (SImode, addr)));
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emit_insn (gen_movsf (gen_rtx_REG (SFmode, i),
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gen_rtx_MEM (SFmode, addr)));
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}
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/* If we were using the restore_a1 strategy and the number of
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@ -1261,8 +1274,8 @@ notice_update_cc (rtx body, rtx insn)
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/* The insn is a compare instruction. */
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CC_STATUS_INIT;
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cc_status.value1 = SET_SRC (body);
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if (GET_CODE (cc_status.value1) == COMPARE
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&& GET_MODE (XEXP (cc_status.value1, 0)) == SFmode)
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if (GET_CODE (SET_SRC (body)) == COMPARE
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&& GET_MODE (XEXP (SET_SRC (body), 0)) == SFmode)
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cc_status.mdep.fpCC = 1;
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break;
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@ -2138,7 +2151,7 @@ mn10300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed ATTRI
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bool
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mn10300_wide_const_load_uses_clr (rtx operands[2])
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{
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long val[2];
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long val[2] = {0, 0};
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if (GET_CODE (operands[0]) != REG
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|| REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS)
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@ -117,7 +117,7 @@ extern enum processor_type mn10300_processor;
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All registers that the compiler knows about must be given numbers,
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even those that are not normally considered general registers. */
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#define FIRST_PSEUDO_REGISTER 50
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#define FIRST_PSEUDO_REGISTER 51
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/* Specify machine-specific register numbers. */
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#define FIRST_DATA_REGNUM 0
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@ -128,6 +128,7 @@ extern enum processor_type mn10300_processor;
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#define LAST_EXTENDED_REGNUM 17
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#define FIRST_FP_REGNUM 18
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#define LAST_FP_REGNUM 49
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#define MDR_REGNUM 50
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#define FIRST_ARGUMENT_REGNUM 0
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/* Specify the registers used for certain standard purposes.
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@ -153,7 +154,7 @@ extern enum processor_type mn10300_processor;
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#define FIXED_REGISTERS \
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{ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 \
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, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
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, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
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, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
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}
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/* 1 for registers not available across function calls.
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@ -167,7 +168,7 @@ extern enum processor_type mn10300_processor;
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#define CALL_USED_REGISTERS \
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{ 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 \
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, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
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, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
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, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
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}
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/* Note: The definition of CALL_REALLY_USED_REGISTERS is not
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@ -298,7 +299,7 @@ enum reg_class {
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{ 0xfffc0000, 0x3ffff }, /* FP_REGS */ \
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{ 0x03fc0000, 0 }, /* FP_ACC_REGS */ \
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{ 0x3fdff, 0 }, /* GENERAL_REGS */ \
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{ 0xffffffff, 0x3ffff } /* ALL_REGS */ \
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{ 0xffffffff, 0x7ffff } /* ALL_REGS */ \
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}
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/* The following macro defines cover classes for Integrated Register
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@ -587,6 +588,8 @@ struct cum_arg {int nbytes; };
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((COUNT == 0) \
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? gen_rtx_MEM (Pmode, arg_pointer_rtx) \
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: (rtx) 0)
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#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, MDR_REGNUM)
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/* Maximum number of registers that can appear in a valid memory address. */
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@ -765,7 +768,7 @@ struct cum_arg {int nbytes; };
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, "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" \
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, "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15" \
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, "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23" \
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, "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31" \
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, "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31", "mdr" \
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}
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#define ADDITIONAL_REGISTER_NAMES \
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@ -810,8 +813,9 @@ struct cum_arg {int nbytes; };
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#define DEFAULT_GDB_EXTENSIONS 1
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/* Use dwarf2 debugging info by default. */
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#undef PREFERRED_DEBUGGING_TYPE
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#undef PREFERRED_DEBUGGING_TYPE
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#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
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#define DWARF2_DEBUGGING_INFO 1
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#define DWARF2_ASM_LINE_DEBUG_INFO 1
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