aarch64: Add Demeter tuning structs
This patch adds tuning structs for -mcpu/-mtune=demeter. gcc/ChangeLog: 2022-03-22 Tamar Christina <tamar.christina@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/aarch64/aarch64.cc (demeter_addrcost_table, demeter_regmove_cost, demeter_advsimd_vector_cost, demeter_sve_vector_cost, demeter_scalar_issue_info, demeter_advsimd_issue_info, demeter_sve_issue_info, demeter_vec_issue_info, demeter_vector_cost, demeter_tunings): New tuning structs. (aarch64_ve_op_count::rename_cycles_per_iter): Enable for demeter tuning. * config/aarch64/aarch64-cores.def: Add entry for demeter. * config/aarch64/aarch64-tune.md (tune): Add demeter to list.
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Andre Vieira
parent
b074fa6970
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27d8748df5
@ -172,4 +172,6 @@ AARCH64_CORE("cortex-a710", cortexa710, cortexa57, 9A, AARCH64_FL_FOR_ARCH9 |
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AARCH64_CORE("cortex-x2", cortexx2, cortexa57, 9A, AARCH64_FL_FOR_ARCH9 | AARCH64_FL_SVE2_BITPERM | AARCH64_FL_MEMTAG | AARCH64_FL_I8MM | AARCH64_FL_BF16, neoversen2, 0x41, 0xd48, -1)
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AARCH64_CORE("demeter", demeter, cortexa57, 9A, AARCH64_FL_FOR_ARCH9 | AARCH64_FL_I8MM | AARCH64_FL_BF16 | AARCH64_FL_SVE2_BITPERM | AARCH64_FL_RNG | AARCH64_FL_MEMTAG | AARCH64_FL_PROFILE, demeter, 0x41, 0xd4f, -1)
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#undef AARCH64_CORE
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@ -1,5 +1,5 @@
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;; -*- buffer-read-only: t -*-
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;; Generated automatically by gentune.sh from aarch64-cores.def
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(define_attr "tune"
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"cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,neoversen2,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexx2"
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"cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,neoversen2,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexx2,demeter"
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(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
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@ -537,6 +537,24 @@ static const struct cpu_addrcost_table neoversen2_addrcost_table =
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0 /* imm_offset */
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};
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static const struct cpu_addrcost_table demeter_addrcost_table =
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{
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{
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1, /* hi */
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0, /* si */
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0, /* di */
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1, /* ti */
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},
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0, /* pre_modify */
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0, /* post_modify */
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2, /* post_modify_ld3_st3 */
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2, /* post_modify_ld4_st4 */
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0, /* register_offset */
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0, /* register_sextend */
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0, /* register_zextend */
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0 /* imm_offset */
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};
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static const struct cpu_regmove_cost generic_regmove_cost =
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{
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1, /* GP2GP */
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@ -652,6 +670,16 @@ static const struct cpu_regmove_cost neoversen2_regmove_cost =
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2 /* FP2FP */
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};
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static const struct cpu_regmove_cost demeter_regmove_cost =
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{
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1, /* GP2GP */
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/* Spilling to int<->fp instead of memory is recommended so set
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realistic costs compared to memmov_cost. */
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3, /* GP2FP */
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2, /* FP2GP */
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2 /* FP2FP */
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};
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/* Generic costs for Advanced SIMD vector operations. */
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static const advsimd_vec_cost generic_advsimd_vector_cost =
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{
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@ -2391,6 +2419,195 @@ static const struct tune_params neoversen2_tunings =
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&generic_prefetch_tune
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};
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static const advsimd_vec_cost demeter_advsimd_vector_cost =
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{
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2, /* int_stmt_cost */
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2, /* fp_stmt_cost */
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2, /* ld2_st2_permute_cost */
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2, /* ld3_st3_permute_cost */
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3, /* ld4_st4_permute_cost */
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3, /* permute_cost */
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4, /* reduc_i8_cost */
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4, /* reduc_i16_cost */
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2, /* reduc_i32_cost */
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2, /* reduc_i64_cost */
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6, /* reduc_f16_cost */
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3, /* reduc_f32_cost */
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2, /* reduc_f64_cost */
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2, /* store_elt_extra_cost */
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/* This value is just inherited from the Cortex-A57 table. */
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8, /* vec_to_scalar_cost */
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/* This depends very much on what the scalar value is and
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where it comes from. E.g. some constants take two dependent
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instructions or a load, while others might be moved from a GPR.
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4 seems to be a reasonable compromise in practice. */
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4, /* scalar_to_vec_cost */
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4, /* align_load_cost */
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4, /* unalign_load_cost */
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/* Although stores have a latency of 2 and compete for the
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vector pipes, in practice it's better not to model that. */
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1, /* unalign_store_cost */
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1 /* store_cost */
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};
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static const sve_vec_cost demeter_sve_vector_cost =
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{
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{
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2, /* int_stmt_cost */
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2, /* fp_stmt_cost */
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3, /* ld2_st2_permute_cost */
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3, /* ld3_st3_permute_cost */
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4, /* ld4_st4_permute_cost */
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3, /* permute_cost */
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/* Theoretically, a reduction involving 15 scalar ADDs could
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complete in ~3 cycles and would have a cost of 15. [SU]ADDV
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completes in 11 cycles, so give it a cost of 15 + 8. */
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21, /* reduc_i8_cost */
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/* Likewise for 7 scalar ADDs (~2 cycles) vs. 9: 7 + 7. */
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14, /* reduc_i16_cost */
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/* Likewise for 3 scalar ADDs (~2 cycles) vs. 8: 3 + 4. */
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7, /* reduc_i32_cost */
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/* Likewise for 1 scalar ADD (~1 cycles) vs. 2: 1 + 1. */
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2, /* reduc_i64_cost */
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/* Theoretically, a reduction involving 7 scalar FADDs could
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complete in ~6 cycles and would have a cost of 14. FADDV
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completes in 8 cycles, so give it a cost of 14 + 2. */
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16, /* reduc_f16_cost */
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/* Likewise for 3 scalar FADDs (~4 cycles) vs. 6: 6 + 2. */
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8, /* reduc_f32_cost */
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/* Likewise for 1 scalar FADD (~2 cycles) vs. 4: 2 + 2. */
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4, /* reduc_f64_cost */
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2, /* store_elt_extra_cost */
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/* This value is just inherited from the Cortex-A57 table. */
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8, /* vec_to_scalar_cost */
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/* See the comment above the Advanced SIMD versions. */
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4, /* scalar_to_vec_cost */
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4, /* align_load_cost */
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4, /* unalign_load_cost */
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/* Although stores have a latency of 2 and compete for the
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vector pipes, in practice it's better not to model that. */
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1, /* unalign_store_cost */
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1 /* store_cost */
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},
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3, /* clast_cost */
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10, /* fadda_f16_cost */
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6, /* fadda_f32_cost */
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4, /* fadda_f64_cost */
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/* A strided Advanced SIMD x64 load would take two parallel FP loads
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(8 cycles) plus an insertion (2 cycles). Assume a 64-bit SVE gather
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is 1 cycle more. The Advanced SIMD version is costed as 2 scalar loads
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(cost 8) and a vec_construct (cost 2). Add a full vector operation
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(cost 2) to that, to avoid the difference being lost in rounding.
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There is no easy comparison between a strided Advanced SIMD x32 load
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and an SVE 32-bit gather, but cost an SVE 32-bit gather as 1 vector
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operation more than a 64-bit gather. */
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14, /* gather_load_x32_cost */
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12, /* gather_load_x64_cost */
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3 /* scatter_store_elt_cost */
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};
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static const aarch64_scalar_vec_issue_info demeter_scalar_issue_info =
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{
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3, /* loads_stores_per_cycle */
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2, /* stores_per_cycle */
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6, /* general_ops_per_cycle */
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0, /* fp_simd_load_general_ops */
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1 /* fp_simd_store_general_ops */
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};
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static const aarch64_advsimd_vec_issue_info demeter_advsimd_issue_info =
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{
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{
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3, /* loads_stores_per_cycle */
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2, /* stores_per_cycle */
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4, /* general_ops_per_cycle */
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0, /* fp_simd_load_general_ops */
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1 /* fp_simd_store_general_ops */
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},
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2, /* ld2_st2_general_ops */
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2, /* ld3_st3_general_ops */
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3 /* ld4_st4_general_ops */
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};
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static const aarch64_sve_vec_issue_info demeter_sve_issue_info =
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{
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{
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{
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3, /* loads_per_cycle */
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2, /* stores_per_cycle */
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4, /* general_ops_per_cycle */
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0, /* fp_simd_load_general_ops */
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1 /* fp_simd_store_general_ops */
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},
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2, /* ld2_st2_general_ops */
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3, /* ld3_st3_general_ops */
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3 /* ld4_st4_general_ops */
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},
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2, /* pred_ops_per_cycle */
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2, /* while_pred_ops */
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2, /* int_cmp_pred_ops */
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1, /* fp_cmp_pred_ops */
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1, /* gather_scatter_pair_general_ops */
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1 /* gather_scatter_pair_pred_ops */
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};
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static const aarch64_vec_issue_info demeter_vec_issue_info =
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{
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&demeter_scalar_issue_info,
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&demeter_advsimd_issue_info,
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&demeter_sve_issue_info
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};
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/* Demeter costs for vector insn classes. */
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static const struct cpu_vector_cost demeter_vector_cost =
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{
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1, /* scalar_int_stmt_cost */
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2, /* scalar_fp_stmt_cost */
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4, /* scalar_load_cost */
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1, /* scalar_store_cost */
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1, /* cond_taken_branch_cost */
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1, /* cond_not_taken_branch_cost */
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&demeter_advsimd_vector_cost, /* advsimd */
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&demeter_sve_vector_cost, /* sve */
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&demeter_vec_issue_info /* issue_info */
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};
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static const struct tune_params demeter_tunings =
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{
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&cortexa76_extra_costs,
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&demeter_addrcost_table,
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&demeter_regmove_cost,
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&demeter_vector_cost,
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&generic_branch_cost,
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&generic_approx_modes,
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SVE_128, /* sve_width */
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{ 4, /* load_int. */
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2, /* store_int. */
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6, /* load_fp. */
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1, /* store_fp. */
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6, /* load_pred. */
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2 /* store_pred. */
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}, /* memmov_cost. */
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5, /* issue_rate */
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(AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_CMP_BRANCH), /* fusible_ops */
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"32:16", /* function_align. */
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"4", /* jump_align. */
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"32:16", /* loop_align. */
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3, /* int_reassoc_width. */
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6, /* fp_reassoc_width. */
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3, /* vec_reassoc_width. */
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2, /* min_div_recip_mul_sf. */
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2, /* min_div_recip_mul_df. */
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0, /* max_case_values. */
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tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */
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(AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND
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| AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
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| AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
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| AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT), /* tune_flags. */
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&generic_prefetch_tune
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};
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static const struct tune_params a64fx_tunings =
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{
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&a64fx_extra_costs,
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@ -15304,7 +15521,8 @@ fractional_cost
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aarch64_vec_op_count::rename_cycles_per_iter () const
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{
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if (sve_issue_info () == &neoverse512tvb_sve_issue_info
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|| sve_issue_info () == &neoversen2_sve_issue_info)
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|| sve_issue_info () == &neoversen2_sve_issue_info
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|| sve_issue_info () == &demeter_sve_issue_info)
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/* + 1 for an addition. We've already counted a general op for each
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store, so we don't need to account for stores separately. The branch
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reads no registers and so does not need to be counted either.
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