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expr.c (expand_expr_real_1): Use expand_insn for movmisalign. 

gcc/
	* expr.c (expand_expr_real_1): Use expand_insn for movmisalign.

From-SVN: r176150
This commit is contained in:
Richard Sandiford 2011-07-11 12:11:33 +00:00 committed by Richard Sandiford
parent f305422365
commit 28164eedaf
2 changed files with 22 additions and 21 deletions
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4
gcc/ChangeLog
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@ -1,3 +1,7 @@
2011-07-11 Richard Sandiford <richard.sandiford@linaro.org>
* expr.c (expand_expr_real_1): Use expand_insn for movmisalign.
2011-07-11 Arthur Loiret <aloiret@debian.org>
* config.gcc (s390-*-linux*): If 'enabled_targets' is 'all', build

39
gcc/expr.c
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@ -8692,7 +8692,8 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode,
{
addr_space_t as = TYPE_ADDR_SPACE (TREE_TYPE (exp));
struct mem_address addr;
int icode, align;
enum insn_code icode;
int align;
get_address_description (exp, &addr);
op0 = addr_for_mem_ref (&addr, as, true);
@ -8709,18 +8710,15 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode,
&& ((icode = optab_handler (movmisalign_optab, mode))
!= CODE_FOR_nothing))
{
rtx reg, insn;
struct expand_operand ops[2];
/* We've already validated the memory, and we're creating a
new pseudo destination. The predicates really can't fail. */
reg = gen_reg_rtx (mode);
/* Nor can the insn generator. */
insn = GEN_FCN (icode) (reg, temp);
gcc_assert (insn != NULL_RTX);
emit_insn (insn);
return reg;
new pseudo destination. The predicates really can't fail,
nor can the generator. */
create_output_operand (&ops[0], NULL_RTX, mode);
create_fixed_operand (&ops[1], temp);
expand_insn (icode, 2, ops);
return ops[0].value;
}
return temp;
}
@ -8732,7 +8730,8 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode,
enum machine_mode address_mode;
tree base = TREE_OPERAND (exp, 0);
gimple def_stmt;
int icode, align;
enum insn_code icode;
int align;
/* Handle expansion of non-aliased memory with non-BLKmode. That
might end up in a register. */
if (TREE_CODE (base) == ADDR_EXPR)
@ -8806,17 +8805,15 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode,
&& ((icode = optab_handler (movmisalign_optab, mode))
!= CODE_FOR_nothing))
{
rtx reg, insn;
struct expand_operand ops[2];
/* We've already validated the memory, and we're creating a
new pseudo destination. The predicates really can't fail. */
reg = gen_reg_rtx (mode);
/* Nor can the insn generator. */
insn = GEN_FCN (icode) (reg, temp);
emit_insn (insn);
return reg;
new pseudo destination. The predicates really can't fail,
nor can the generator. */
create_output_operand (&ops[0], NULL_RTX, mode);
create_fixed_operand (&ops[1], temp);
expand_insn (icode, 2, ops);
return ops[0].value;
}
return temp;
}