Michael Hayes
Michael Hayes
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314451260e
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282a61e662
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@ -1,3 +1,7 @@
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Wed Jun 9 22:57:02 1999 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
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* invoke.texi: Add C4x invocation docs.
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Wed Jun 9 22:34:38 1999 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
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* config/c4x/c4x.h (TARGET_EXPOSE_LDP, LEGITIMIZE_RELOAD_ADDRESS):
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131
gcc/invoke.texi
131
gcc/invoke.texi
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@ -393,6 +393,12 @@ in the following sections.
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-mmangle-cpu -mcpu=@var{cpu} -mtext=@var{text section}
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-mdata=@var{data section} -mrodata=@var{readonly data section}
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@emph{TMS320C3x/C4x Options}
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-mcpu=@var{cpu} -mbig -msmall -mregparm -mmemparm
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-mfast-fix -mmpyi -mbk -mti -mdp-isr-reload
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-mrpts=@var{count} -mrptb -mdb -mloop-unsigned
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-mparallel-insns -mparallel-mpy -mpreserve-float
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@emph{V850 Options}
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-mlong-calls -mno-long-calls -mep -mno-ep
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-mprolog-function -mno-prolog-function -mspace
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@ -3110,6 +3116,7 @@ that macro, which enables you to change the defaults.
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* H8/300 Options::
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* SH Options::
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* System V Options::
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* TMS320C3x/C4x Options::
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* V850 Options::
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* ARC Options::
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* NS32K Options::
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@ -5749,6 +5756,130 @@ The assembler uses this option.
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@c the generic assembler that comes with Solaris takes just -Ym.
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@end table
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@node TMS320C3x/C4x Options
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@subsection TMS320C3x/C4x Options
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@cindex TMS320C3x/C4x Options
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These @samp{-m} options are defined for TMS320C3x/C4x implementations:
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@table @code
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@item -mcpu=@var{cpu_type}
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Set the instruction set, register set, and instruction scheduling
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parameters for machine type @var{cpu_type}. Supported values for
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@var{cpu_type} are @samp{c30}, @samp{c31}, @samp{c32}, @samp{c40}, and
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@samp{c44}. The default is @samp{c40} to generate code for the
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TMS320C40.
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@item -mbig-memory
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@item -mbig
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@itemx -msmall-memory
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@itemx -msmall
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Generates code for the big or small memory model. The small memory
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model assumed that all data fits into one 64K word page. At run-time
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the data page (DP) register must be set to point to the 64K page
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containing the .bss and .data program sections. The big memory model is
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the default and requires reloading of the DP register for every direct
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memory access.
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@item -mbk
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@itemx -mno-bk
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Allow (disallow) allocation of general integer operands into the block
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count register BK.
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@item -mdb
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@itemx -mno-db
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Enable (disable) generation of code using decrement and branch,
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DBcond(D), instructions. This is enabled by default for the C4x. To be
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on the safe side, this is disabled for the C3x, since the maximum
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iteration count on the C3x is 2^23 + 1 (but who iterates loops more than
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2^23 times on the C3x?). Note that GCC will try to reverse a loop so
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that it can utilise the decrement and branch instruction, but will give
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up if there is more than one memory reference in the loop. Thus a loop
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where the loop counter is decremented can generate slightly more
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efficient code, in cases where the RPTB instruction cannot be utilised.
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@item -mdp-isr-reload
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@itemx -mparanoid
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Force the DP register to be saved on entry to an interrupt service
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routine (ISR), reloaded to point to the data section, and restored on
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exit from the ISR. This should not be required unless someone has
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violated the small memory model by modifying the DP register, say within
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an object library.
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@item -mmpyi
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@itemx -mno-mpyi
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For the C3x use the 24-bit MPYI instruction for integer multiplies
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instead of a library call to guarantee 32-bit results. Note that if one
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of the operands is a constant, then the multiplication will be performed
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using shifts and adds. If the -mmpyi option is not specified for the C3x,
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then squaring operations are performed inline instead of a library call.
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@item -mfast-fix
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@itemx -mno-fast-fix
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The C3x/C4x FIX instruction to convert a floating point value to an
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integer value chooses the nearest integer less than or equal to the
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floating point value rather than to the nearest integer. Thus if the
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floating point number is negative, the result will be incorrectly
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truncated an additional code is necessary to detect and correct this
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case. This option can be used to disable generation of the additional
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code required to correct the result.
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@item -mrptb
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@itemx -mno-rptb
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Enable (disable) generation of repeat block sequences using the RPTB
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instruction for zero overhead looping. The RPTB construct is only used
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for innermost loops that do not call functions or jump across the loop
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boundaries. There is no advantage having nested RPTB loops due to the
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overhead required to save and restore the RC, RS, and RE registers.
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This is enabled by default with -O2.
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@item -mrpts=@var{count}
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@itemx -mno-rpts
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Enable (disable) the use of the single instruction repeat instruction
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RPTS. If a repeat block contains a single instruction, and the loop
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count can be guaranteed to be less than the value @var{count}, GCC will
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emit a RPTS instruction instead of a RPTB. If no value is specified,
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then a RPTS will be emitted even if the loop count cannot be determined
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at compile time. Note that the repeated instruction following RPTS does
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not have to be reloaded from memory each iteration, thus freeing up the
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CPU buses for oeprands. However, since interrupts are blocked by this
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instruction, it is disabled by default.
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@item -mloop-unsigned
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@itemx -mno-loop-unsigned
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The maximum iteration count when using RPTS and RPTB (and DB on the C40)
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is 2^31 + 1 since these instructions test if the iteration count is
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negative to terminate the loop. If the iteration count is unsigned
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there is a possibility than the 2^31 + 1 maximum iteration count may be
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exceeded. This switch allows an unsigned iteration count.
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@item -mti
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Try to emit an assembler syntax that the TI assembler (asm30) is happy
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with. This also enforces compatibility with the API employed by the TI
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C3x C compiler. For example, long doubles are passed as structures
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rather than in floating point registers.
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@item -mregparm
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@itemx -mmemparm
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Generate code that uses registers (stack) for passing arguments to functions.
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By default, arguments are passed in registers where possible rather
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than by pushing arguments on to the stack.
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@item -mparallel-insns
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@itemx -mno-parallel-insns
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Allow the generation of parallel instructions. This is enabled by
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default with -O2.
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@item -mparallel-mpy
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@itemx -mno-parallel-mpy
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Allow the generation of MPY||ADD and MPY||SUB parallel instructions,
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provided -mparallel-insns is also specified. These instructions have
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tight register constraints which can pessimize the code generation
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of large functions.
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@end table
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@node V850 Options
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@subsection V850 Options
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@cindex V850 Options
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