RISC-V: Implement instruction patterns for ZBA extension.
2021-10-25 Jim Wilson <jimw@sifive.com> Kito Cheng <kito.cheng@sifive.com> Jia-Wei Chen <jiawei@iscas.ac.cn> gcc/ChangeLog: * config/riscv/bitmanip.md (*zero_extendsidi2_bitmanip): New. (*shNadd): Ditto. (*shNadduw): Ditto. (*add.uw): Ditto. (*slliuw): Ditto. (riscv_rtx_costs): Ditto. * config/riscv/riscv.md: Include bitmanip.md (type): Add bitmanip bype. (zero_extendsidi2): Change to define_expand pattern. (*zero_extendsidi2_internal): New. (zero_extendsidi2_shifted): Disable for ZBA. 2021-10-25 Kito Cheng <kito.cheng@sifive.com> Jia-Wei Chen <jiawei@iscas.ac.cn> gcc/testsuite/ChangeLog: * gcc.target/riscv/zba-adduw.c: New. * gcc.target/riscv/zba-shNadd-01.c: Ditto. * gcc.target/riscv/zba-shNadd-02.c: Ditto. * gcc.target/riscv/zba-shNadd-03.c: Ditto. * gcc.target/riscv/zba-slliuw.c: Ditto. * gcc.target/riscv/zba-zextw.c: Ditto. Co-authored-by: Kito Cheng <kito.cheng@sifive.com> Co-authored-by: Jia-Wei Chen <jiawei@iscas.ac.cn>
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;; Machine description for RISC-V Bit Manipulation operations.
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;; Copyright (C) 2021 Free Software Foundation, Inc.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; ZBA extension.
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(define_insn "*zero_extendsidi2_bitmanip"
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
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"TARGET_64BIT && TARGET_ZBA"
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"@
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zext.w\t%0,%1
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lwu\t%0,%1"
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[(set_attr "type" "bitmanip,load")
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(set_attr "mode" "DI")])
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(define_insn "*shNadd"
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[(set (match_operand:X 0 "register_operand" "=r")
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(plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
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(match_operand:QI 2 "immediate_operand" "I"))
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(match_operand:X 3 "register_operand" "r")))]
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"TARGET_ZBA
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&& (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)"
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"sh%2add\t%0,%1,%3"
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[(set_attr "type" "bitmanip")
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(set_attr "mode" "<X:MODE>")])
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(define_insn "*shNadduw"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(plus:DI
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(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:QI 2 "immediate_operand" "I"))
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(match_operand 3 "immediate_operand" ""))
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(match_operand:DI 4 "register_operand" "r")))]
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"TARGET_64BIT && TARGET_ZBA
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&& (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
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&& (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
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"sh%2add.uw\t%0,%1,%4"
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[(set_attr "type" "bitmanip")
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(set_attr "mode" "DI")])
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(define_insn "*add.uw"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(plus:DI (zero_extend:DI
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(match_operand:SI 1 "register_operand" "r"))
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(match_operand:DI 2 "register_operand" "r")))]
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"TARGET_64BIT && TARGET_ZBA"
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"add.uw\t%0,%1,%2"
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[(set_attr "type" "bitmanip")
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(set_attr "mode" "DI")])
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(define_insn "*slliuw"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:QI 2 "immediate_operand" "I"))
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(match_operand 3 "immediate_operand" "")))]
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"TARGET_64BIT && TARGET_ZBA
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&& (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
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"slli.uw\t%0,%1,%2"
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[(set_attr "type" "bitmanip")
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(set_attr "mode" "DI")])
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@ -170,7 +170,7 @@
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(define_attr "type"
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"unknown,branch,jump,call,load,fpload,store,fpstore,
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mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
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fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost"
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fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip"
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(cond [(eq_attr "got" "load") (const_string "load")
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;; If a doubleword move uses these expensive instructions,
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@ -1302,11 +1302,16 @@
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;; Extension insns.
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(define_insn_and_split "zero_extendsidi2"
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(define_expand "zero_extendsidi2"
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[(set (match_operand:DI 0 "register_operand")
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(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
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"TARGET_64BIT")
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(define_insn_and_split "*zero_extendsidi2_internal"
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(zero_extend:DI
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(match_operand:SI 1 "nonimmediate_operand" " r,m")))]
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"TARGET_64BIT"
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"TARGET_64BIT && !(TARGET_ZBA || TARGET_ZBB)"
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"@
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#
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lwu\t%0,%1"
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@ -2078,7 +2083,7 @@
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(match_operand:QI 2 "immediate_operand" "I"))
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(match_operand 3 "immediate_operand" "")))
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(clobber (match_scratch:DI 4 "=&r"))]
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"TARGET_64BIT
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"TARGET_64BIT && !TARGET_ZBA
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&& ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)"
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"#"
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"&& reload_completed"
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@ -2845,6 +2850,7 @@
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"<load>\t%3, %1\;<load>\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0"
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[(set_attr "length" "12")])
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(include "bitmanip.md")
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(include "sync.md")
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(include "peephole.md")
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(include "pic.md")
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
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int foo(int n, unsigned char *arr, unsigned y){
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int s = 0;
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unsigned x = 0;
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for (;x<n;x++)
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s += arr[x+y];
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return s;
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}
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/* { dg-final { scan-assembler "add.uw" } } */
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
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long test_1(long a, long b)
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{
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return a + (b << 1);
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}
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long test_2(long a, long b)
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{
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return a + (b << 2);
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}
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long test_3(long a, long b)
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{
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return a + (b << 3);
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}
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/* { dg-final { scan-assembler-times "sh1add" 1 } } */
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/* { dg-final { scan-assembler-times "sh2add" 1 } } */
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/* { dg-final { scan-assembler-times "sh3add" 1 } } */
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/* { dg-do compile } */
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/* { dg-options "-march=rv32gc_zba -mabi=ilp32 -O2" } */
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long test_1(long a, long b)
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{
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return a + (b << 1);
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}
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long test_2(long a, long b)
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{
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return a + (b << 2);
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}
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long test_3(long a, long b)
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{
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return a + (b << 3);
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}
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/* { dg-final { scan-assembler-times "sh1add" 1 } } */
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/* { dg-final { scan-assembler-times "sh2add" 1 } } */
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/* { dg-final { scan-assembler-times "sh3add" 1 } } */
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
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/* RV64 only. */
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int foos(short *x, int n){
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return x[n];
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}
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int fooi(int *x, int n){
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return x[n];
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}
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int fooll(long long *x, int n){
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return x[n];
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}
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/* RV64 only. */
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int ufoos(short *x, unsigned int n){
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return x[n];
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}
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int ufooi(int *x, unsigned int n){
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return x[n];
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}
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int ufooll(long long *x, unsigned int n){
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return x[n];
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}
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/* { dg-final { scan-assembler-times "sh1add\t" 1 } } */
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/* { dg-final { scan-assembler-times "sh2add\t" 1 } } */
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/* { dg-final { scan-assembler-times "sh3add\t" 1 } } */
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/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */
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/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */
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/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
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long
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foo (long i)
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{
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return (long)(unsigned int)i << 10;
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}
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/* XXX: This pattern need combine improvement or intermediate instruction
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* from zbs. */
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/* { dg-final { scan-assembler-not "slli.uw" } } */
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@ -0,0 +1,10 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
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long
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foo (long i)
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{
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return (long)(unsigned int)i;
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}
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/* XXX: This pattern require combine improvement. */
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/* { dg-final { scan-assembler-not "slli.uw" } } */
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