[AArch64] Revert "Improve TLS Descriptor pattern to release RTL loop IV opt"
2015-09-28 Jiong Wang <jiong.wang@arm.com> Revert: 2015-08-06 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> Jiong Wang <jiong.wang@arm.com> * config/aarch64/aarch64.d (tlsdesc_small_pseudo_<mode>): New pattern. * config/aarch64/aarch64.h (reg_class): New enumeration FIXED_REG0. (REG_CLASS_NAMES): Likewise. (REG_CLASS_CONTENTS): Likewise. * config/aarch64/aarch64.c (aarch64_class_max_nregs): Likewise. (aarch64_register_move_cost): Likewise. (aarch64_load_symref_appropriately): Invoke the new added pattern if possible. * config/aarch64/constraints.md (Uc0): New constraint. From-SVN: r228211
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Jiong Wang
Jiong Wang
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@ -1,3 +1,19 @@
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2015-09-28 Jiong Wang <jiong.wang@arm.com>
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Revert:
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2015-08-06 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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Jiong Wang <jiong.wang@arm.com>
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* config/aarch64/aarch64.d (tlsdesc_small_pseudo_<mode>): New pattern.
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* config/aarch64/aarch64.h (reg_class): New enumeration FIXED_REG0.
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(REG_CLASS_NAMES): Likewise.
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(REG_CLASS_CONTENTS): Likewise.
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* config/aarch64/aarch64.c (aarch64_class_max_nregs): Likewise.
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(aarch64_register_move_cost): Likewise.
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(aarch64_load_symref_appropriately): Invoke the new added pattern if
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possible.
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* config/aarch64/constraints.md (Uc0): New constraint.
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2015-09-28 Daniel Hellstrom <daniel@gaisler.com>
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* config/sparc/t-rtems: Remove -muser-mode. Add ut699, at697f and leon.
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@ -1061,39 +1061,22 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
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{
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machine_mode mode = GET_MODE (dest);
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rtx x0 = gen_rtx_REG (mode, R0_REGNUM);
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rtx offset;
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rtx tp;
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gcc_assert (mode == Pmode || mode == ptr_mode);
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if (can_create_pseudo_p ())
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{
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rtx reg = gen_reg_rtx (mode);
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if (TARGET_ILP32)
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emit_insn (gen_tlsdesc_small_pseudo_si (reg, imm));
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else
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emit_insn (gen_tlsdesc_small_pseudo_di (reg, imm));
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offset = reg;
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}
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/* In ILP32, the got entry is always of SImode size. Unlike
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small GOT, the dest is fixed at reg 0. */
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if (TARGET_ILP32)
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emit_insn (gen_tlsdesc_small_si (imm));
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else
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{
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/* In ILP32, the got entry is always of SImode size. Unlike
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small GOT, the dest is fixed at reg 0. */
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if (TARGET_ILP32)
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emit_insn (gen_tlsdesc_small_si (imm));
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else
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emit_insn (gen_tlsdesc_small_di (imm));
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offset = x0;
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}
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emit_insn (gen_tlsdesc_small_di (imm));
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tp = aarch64_load_tp (NULL);
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if (mode != Pmode)
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tp = gen_lowpart (mode, tp);
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emit_insn (gen_rtx_SET (dest, gen_rtx_PLUS (mode, tp, offset)));
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emit_insn (gen_rtx_SET (dest, gen_rtx_PLUS (mode, tp, x0)));
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set_unique_reg_note (get_last_insn (), REG_EQUIV, imm);
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return;
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}
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@ -5084,7 +5067,6 @@ aarch64_class_max_nregs (reg_class_t regclass, machine_mode mode)
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aarch64_vector_mode_p (mode)
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? (GET_MODE_SIZE (mode) + UNITS_PER_VREG - 1) / UNITS_PER_VREG
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: (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
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case FIXED_REG0:
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case STACK_REG:
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return 1;
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@ -6972,10 +6954,10 @@ aarch64_register_move_cost (machine_mode mode,
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= aarch64_tune_params.regmove_cost;
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/* Caller save and pointer regs are equivalent to GENERAL_REGS. */
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if (to == CALLER_SAVE_REGS || to == POINTER_REGS || to == FIXED_REG0)
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if (to == CALLER_SAVE_REGS || to == POINTER_REGS)
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to = GENERAL_REGS;
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if (from == CALLER_SAVE_REGS || from == POINTER_REGS || from == FIXED_REG0)
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if (from == CALLER_SAVE_REGS || from == POINTER_REGS)
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from = GENERAL_REGS;
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/* Moving between GPR and stack cost is the same as GP2GP. */
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@ -405,7 +405,6 @@ extern unsigned aarch64_architecture_version;
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enum reg_class
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{
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NO_REGS,
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FIXED_REG0,
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CALLER_SAVE_REGS,
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GENERAL_REGS,
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STACK_REG,
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@ -421,7 +420,6 @@ enum reg_class
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#define REG_CLASS_NAMES \
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{ \
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"NO_REGS", \
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"FIXED_REG0", \
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"CALLER_SAVE_REGS", \
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"GENERAL_REGS", \
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"STACK_REG", \
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@ -434,7 +432,6 @@ enum reg_class
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#define REG_CLASS_CONTENTS \
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{ \
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{ 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
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{ 0x00000001, 0x00000000, 0x00000000 }, /* FIXED_REG0 */ \
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{ 0x0007ffff, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \
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{ 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \
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{ 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
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@ -4773,25 +4773,6 @@
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[(set_attr "type" "call")
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(set_attr "length" "16")])
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;; The same as tlsdesc_small_<mode> with hard register hiding.
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;; The first operand is actually x0, while we wrap it under a delicated
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;; register class so that before register allocation, it's seen as pseudo
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;; register. The reason for doing this is we don't expose hard register X0
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;; as the destination of set as it will cause trouble for RTL loop iv.
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;; RTL loop iv will abort ongoing optimization once it finds there is hard reg
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;; as destination of set.
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(define_insn "tlsdesc_small_pseudo_<mode>"
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[(set (match_operand:PTR 0 "register_operand" "=Uc0")
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(unspec:PTR [(match_operand 1 "aarch64_valid_symref" "S")]
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UNSPEC_TLSDESC))
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(clobber (reg:DI LR_REGNUM))
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(clobber (reg:CC CC_REGNUM))
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(clobber (match_scratch:DI 2 "=r"))]
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"TARGET_TLS_DESC"
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"adrp\\t<w>0, %A1\;ldr\\t%<w>2, [%<w>0, #%L1]\;add\\t%<w>0, %<w>0, %L1\;.tlsdesccall\\t%1\;blr\\t%2"
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[(set_attr "type" "call")
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(set_attr "length" "16")])
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(define_insn "stack_tie"
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[(set (mem:BLK (scratch))
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(unspec:BLK [(match_operand:DI 0 "register_operand" "rk")
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@ -24,9 +24,6 @@
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(define_register_constraint "Ucs" "CALLER_SAVE_REGS"
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"@internal The caller save registers.")
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(define_register_constraint "Uc0" "FIXED_REG0"
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"@internal Represent X0/W0.")
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(define_register_constraint "w" "FP_REGS"
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"Floating point and SIMD vector registers.")
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@ -1,22 +0,0 @@
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/* { dg-do compile } */
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/* { dg-require-effective-target tls_native } */
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/* { dg-options "-O2 -fpic -fdump-rtl-loop2_invariant" } */
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/* { dg-skip-if "-mcmodel=large, no support for -fpic" { aarch64-*-* } { "-mcmodel=large" } { "" } } */
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int cal (int, int);
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__thread int tls_data;
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int
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foo (int bound)
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{
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int i = 0;
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int sum = 0;
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for (i; i < bound; i++)
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sum = cal (sum, tls_data);
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return sum;
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}
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/* Insn sequences for TLS descriptor should be hoisted out of the loop. */
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/* { dg-final { scan-rtl-dump "Decided" "loop2_invariant" } } */
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