bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add D0REGS through D7REGS. (CONSTRAINT_LEN): Add entry for 'q'. (REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER. Add 'q' constraints. (REGNO_REG_CLASS): For R0 through R7, return corresponding regclass. (CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2. * config/bfin/bfin.md (add_with_carry): New pattern. (s_or_u, su_optab, su_modifier): New code macros/attrs. (<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl, <su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to support unsigned multiplies too. Removed incorrect commutativity from operand 1 constraint where appropriate. (usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New patterns. (<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh, <su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh): New patterns. (usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul, usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul, usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul, usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul, usmulhisi_hh_huh): New patterns. From-SVN: r122373
This commit is contained in:
Bernd Schmidt
Bernd Schmidt
parent
ce27ef3d72
commit
2889abeda3
@ -15,6 +15,31 @@
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(bfin_reorder_loops): New function.
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(bfin_reorg_loops): Use these three new functions.
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* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
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REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
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(CONSTRAINT_LEN): Add entry for 'q'.
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(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
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Add 'q' constraints.
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(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
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(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
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* config/bfin/bfin.md (add_with_carry): New pattern.
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(s_or_u, su_optab, su_modifier): New code macros/attrs.
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(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
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<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
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support unsigned multiplies too. Removed incorrect commutativity from
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operand 1 constraint where appropriate.
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(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
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patterns.
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(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
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<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
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New patterns.
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(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
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usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
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usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
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usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
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usmulhisi_hh_huh): New patterns.
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2007-02-27 Andreas Schwab <schwab@suse.de>
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* Makefile.in (TEXI_GCCINSTALL_FILES): Add gcc-common.texi.
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@ -411,6 +411,14 @@ enum reg_class
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CCREGS,
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EVEN_DREGS,
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ODD_DREGS,
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D0REGS,
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D1REGS,
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D2REGS,
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D3REGS,
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D4REGS,
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D5REGS,
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D6REGS,
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D7REGS,
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DREGS,
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FDPIC_REGS,
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FDPIC_FPTR_REGS,
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@ -447,6 +455,14 @@ enum reg_class
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"CCREGS", \
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"EVEN_DREGS", \
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"ODD_DREGS", \
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"D0REGS", \
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"D1REGS", \
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"D2REGS", \
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"D3REGS", \
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"D4REGS", \
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"D5REGS", \
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"D6REGS", \
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"D7REGS", \
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"DREGS", \
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"FDPIC_REGS", \
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"FDPIC_FPTR_REGS", \
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@ -491,6 +507,14 @@ enum reg_class
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{ 0x00000000, 0x4 }, /* CCREGS */ \
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{ 0x00000055, 0 }, /* EVEN_DREGS */ \
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{ 0x000000aa, 0 }, /* ODD_DREGS */ \
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{ 0x00000001, 0 }, /* D0REGS */ \
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{ 0x00000002, 0 }, /* D1REGS */ \
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{ 0x00000004, 0 }, /* D2REGS */ \
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{ 0x00000008, 0 }, /* D3REGS */ \
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{ 0x00000010, 0 }, /* D4REGS */ \
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{ 0x00000020, 0 }, /* D5REGS */ \
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{ 0x00000040, 0 }, /* D6REGS */ \
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{ 0x00000080, 0 }, /* D7REGS */ \
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{ 0x000000ff, 0 }, /* DREGS */ \
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{ 0x00000800, 0x000 }, /* FDPIC_REGS */ \
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{ 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
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@ -537,7 +561,7 @@ enum reg_class
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/* Get reg_class from a letter such as appears in the machine description. */
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#define REG_CLASS_FROM_LETTER(LETTER) \
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#define REG_CLASS_FROM_CONSTRAINT(LETTER, STR) \
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((LETTER) == 'a' ? PREGS : \
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(LETTER) == 'Z' ? FDPIC_REGS : \
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(LETTER) == 'Y' ? FDPIC_FPTR_REGS : \
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@ -559,6 +583,16 @@ enum reg_class
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(LETTER) == 'x' ? MOST_REGS : \
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(LETTER) == 'y' ? PROLOGUE_REGS : \
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(LETTER) == 'w' ? NON_A_CC_REGS : \
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(LETTER) == 'q' \
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? ((STR)[1] == '0' ? D0REGS \
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: (STR)[1] == '1' ? D1REGS \
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: (STR)[1] == '2' ? D2REGS \
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: (STR)[1] == '3' ? D3REGS \
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: (STR)[1] == '4' ? D4REGS \
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: (STR)[1] == '5' ? D5REGS \
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: (STR)[1] == '6' ? D6REGS \
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: (STR)[1] == '7' ? D7REGS \
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: NO_REGS) : \
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NO_REGS)
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/* The same information, inverted:
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@ -567,7 +601,14 @@ enum reg_class
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or could index an array. */
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#define REGNO_REG_CLASS(REGNO) \
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((REGNO) < REG_P0 ? DREGS \
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((REGNO) == REG_R0 ? D0REGS \
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: (REGNO) == REG_R1 ? D1REGS \
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: (REGNO) == REG_R2 ? D2REGS \
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: (REGNO) == REG_R3 ? D3REGS \
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: (REGNO) == REG_R4 ? D4REGS \
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: (REGNO) == REG_R5 ? D5REGS \
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: (REGNO) == REG_R6 ? D6REGS \
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: (REGNO) == REG_R7 ? D7REGS \
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: (REGNO) < REG_I0 ? PREGS \
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: (REGNO) == REG_ARGP ? PREGS \
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: (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
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@ -590,6 +631,9 @@ enum reg_class
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#define CLASS_LIKELY_SPILLED_P(CLASS) \
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((CLASS) == PREGS_CLOBBERED \
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|| (CLASS) == PROLOGUE_REGS \
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|| (CLASS) == D0REGS \
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|| (CLASS) == D1REGS \
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|| (CLASS) == D2REGS \
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|| (CLASS) == CCREGS)
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/* Do not allow to store a value in REG_CC for any mode */
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@ -1030,7 +1074,7 @@ do { \
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#define CONST_3UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 7)
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#define CONSTRAINT_LEN(C, STR) \
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((C) == 'P' || (C) == 'M' || (C) == 'N' ? 2 \
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((C) == 'P' || (C) == 'M' || (C) == 'N' || (C) == 'q' ? 2 \
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: (C) == 'K' ? 3 \
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: DEFAULT_CONSTRAINT_LEN ((C), (STR)))
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@ -1007,6 +1007,24 @@
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;; DImode arithmetic operations
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(define_insn "add_with_carry"
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[(set (match_operand:SI 0 "register_operand" "=d,d")
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(plus:SI (match_operand:SI 1 "register_operand" "%0,0")
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(match_operand:SI 2 "nonmemory_operand" "Ks7,d")))
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(set (match_operand:SI 3 "register_operand" "=d,d")
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(truncate:SI
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(lshiftrt:DI (plus:DI (zero_extend:DI (match_dup 1))
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(zero_extend:DI (match_dup 2)))
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(const_int 32))))
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(clobber (reg:CC 34))]
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""
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"@
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%0 += %2; cc = ac0; %3 = cc;
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%0 = %0 + %2; cc = ac0; %3 = cc;"
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[(set_attr "type" "alu0")
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(set_attr "length" "6")
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(set_attr "seq_insns" "multi")])
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(define_insn "adddi3"
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[(set (match_operand:DI 0 "register_operand" "=&d,&d,&d")
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(plus:DI (match_operand:DI 1 "register_operand" "%0,0,0")
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@ -3249,54 +3267,491 @@
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}
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[(set_attr "type" "dsp32")])
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(define_insn "mulhisi_ll"
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(define_code_macro s_or_u [sign_extend zero_extend])
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(define_code_attr su_optab [(sign_extend "mul")
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(zero_extend "umul")])
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(define_code_attr su_modifier [(sign_extend "IS")
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(zero_extend "FU")])
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(define_insn "<su_optab>hisi_ll"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(mult:SI (sign_extend:SI
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(mult:SI (s_or_u:SI
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(vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
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(parallel [(const_int 0)])))
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(s_or_u:SI
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(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
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(parallel [(const_int 0)])))))]
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""
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"%0 = %h1 * %h2 (<su_modifier>)%!"
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[(set_attr "type" "dsp32")])
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(define_insn "<su_optab>hisi_lh"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(mult:SI (s_or_u:SI
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(vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
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(parallel [(const_int 0)])))
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(s_or_u:SI
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(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
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(parallel [(const_int 1)])))))]
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""
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"%0 = %h1 * %d2 (<su_modifier>)%!"
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[(set_attr "type" "dsp32")])
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(define_insn "<su_optab>hisi_hl"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(mult:SI (s_or_u:SI
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(vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
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(parallel [(const_int 1)])))
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(s_or_u:SI
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(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
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(parallel [(const_int 0)])))))]
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""
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"%0 = %d1 * %h2 (<su_modifier>)%!"
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[(set_attr "type" "dsp32")])
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(define_insn "<su_optab>hisi_hh"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(mult:SI (s_or_u:SI
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(vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
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(parallel [(const_int 1)])))
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(s_or_u:SI
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(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
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(parallel [(const_int 1)])))))]
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""
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"%0 = %d1 * %d2 (<su_modifier>)%!"
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[(set_attr "type" "dsp32")])
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;; Additional variants for signed * unsigned multiply.
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(define_insn "usmulhisi_ull"
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[(set (match_operand:SI 0 "register_operand" "=W")
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(mult:SI (zero_extend:SI
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(vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
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(parallel [(const_int 0)])))
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(sign_extend:SI
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(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
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(parallel [(const_int 0)])))))]
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""
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"%0 = %h1 * %h2 (IS)%!"
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"%0 = %h2 * %h1 (IS,M)%!"
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[(set_attr "type" "dsp32")])
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(define_insn "mulhisi_lh"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(mult:SI (sign_extend:SI
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(vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
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(define_insn "usmulhisi_ulh"
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[(set (match_operand:SI 0 "register_operand" "=W")
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(mult:SI (zero_extend:SI
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(vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
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(parallel [(const_int 0)])))
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(sign_extend:SI
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(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
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(parallel [(const_int 1)])))))]
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""
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"%0 = %h1 * %d2 (IS)%!"
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"%0 = %d2 * %h1 (IS,M)%!"
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[(set_attr "type" "dsp32")])
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(define_insn "mulhisi_hl"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(mult:SI (sign_extend:SI
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(vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
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(define_insn "usmulhisi_uhl"
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[(set (match_operand:SI 0 "register_operand" "=W")
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(mult:SI (zero_extend:SI
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(vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
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(parallel [(const_int 1)])))
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(sign_extend:SI
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(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
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(parallel [(const_int 0)])))))]
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""
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"%0 = %d1 * %h2 (IS)%!"
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"%0 = %h2 * %d1 (IS,M)%!"
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[(set_attr "type" "dsp32")])
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(define_insn "mulhisi_hh"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(mult:SI (sign_extend:SI
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(define_insn "usmulhisi_uhh"
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[(set (match_operand:SI 0 "register_operand" "=W")
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(mult:SI (zero_extend:SI
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(vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
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(parallel [(const_int 1)])))
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(sign_extend:SI
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(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
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(parallel [(const_int 1)])))))]
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""
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"%0 = %d1 * %d2 (IS)%!"
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"%0 = %d2 * %d1 (IS,M)%!"
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[(set_attr "type" "dsp32")])
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;; Parallel versions of these operations. First, normal signed or unsigned
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;; multiplies.
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(define_insn "<su_optab>hisi_ll_lh"
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[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
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(mult:SI (s_or_u:SI
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(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
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(parallel [(const_int 0)])))
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(s_or_u:SI
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(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
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(parallel [(const_int 0)])))))
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(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
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(mult:SI (s_or_u:SI
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(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
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(s_or_u:SI
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(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
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""
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"%0 = %h1 * %h2, %3 = %h1 * %d2 (<su_modifier>)%!"
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[(set_attr "type" "dsp32")])
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(define_insn "<su_optab>hisi_ll_hl"
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[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
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(mult:SI (s_or_u:SI
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(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
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(parallel [(const_int 0)])))
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(s_or_u:SI
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(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
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(parallel [(const_int 0)])))))
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(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
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(mult:SI (s_or_u:SI
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(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
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(s_or_u:SI
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(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
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""
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"%0 = %h1 * %h2, %3 = %d1 * %h2 (<su_modifier>)%!"
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[(set_attr "type" "dsp32")])
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(define_insn "<su_optab>hisi_ll_hh"
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[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
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(mult:SI (s_or_u:SI
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(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
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(parallel [(const_int 0)])))
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(s_or_u:SI
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(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
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(parallel [(const_int 0)])))))
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(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
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(mult:SI (s_or_u:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
||||
(s_or_u:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
||||
""
|
||||
"%0 = %h1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "<su_optab>hisi_lh_hl"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (s_or_u:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))
|
||||
(s_or_u:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (s_or_u:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
||||
(s_or_u:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
||||
""
|
||||
"%0 = %h1 * %d2, %3 = %d1 * %h2 (<su_modifier>)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "<su_optab>hisi_lh_hh"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (s_or_u:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))
|
||||
(s_or_u:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (s_or_u:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
||||
(s_or_u:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
||||
""
|
||||
"%0 = %h1 * %d2, %3 = %d1 * %d2 (<su_modifier>)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "<su_optab>hisi_hl_hh"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (s_or_u:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))
|
||||
(s_or_u:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (s_or_u:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
||||
(s_or_u:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
||||
""
|
||||
"%0 = %d1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
;; Special signed * unsigned variants.
|
||||
|
||||
(define_insn "usmulhisi_ll_lul"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
||||
(zero_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
||||
""
|
||||
"%0 = %h1 * %h2, %3 = %h1 * %h2 (IS,M)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "usmulhisi_ll_luh"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
||||
(zero_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
||||
""
|
||||
"%0 = %h1 * %h2, %3 = %h1 * %d2 (IS,M)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "usmulhisi_ll_hul"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
||||
(zero_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
||||
""
|
||||
"%0 = %h1 * %h2, %3 = %d1 * %h2 (IS,M)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "usmulhisi_ll_huh"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
||||
(zero_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
||||
""
|
||||
"%0 = %h1 * %h2, %3 = %d1 * %d2 (IS,M)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "usmulhisi_lh_lul"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
||||
(zero_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
||||
""
|
||||
"%0 = %h1 * %d2, %3 = %h1 * %h2 (IS,M)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "usmulhisi_lh_luh"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
||||
(zero_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
||||
""
|
||||
"%0 = %h1 * %d2, %3 = %h1 * %d2 (IS,M)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "usmulhisi_lh_hul"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
||||
(zero_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
||||
""
|
||||
"%0 = %h1 * %d2, %3 = %d1 * %h2 (IS,M)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "usmulhisi_lh_huh"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
||||
(zero_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
||||
""
|
||||
"%0 = %h1 * %d2, %3 = %d1 * %d2 (IS,M)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "usmulhisi_hl_lul"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
||||
(zero_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
||||
""
|
||||
"%0 = %d1 * %h2, %3 = %h1 * %h2 (IS,M)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "usmulhisi_hl_luh"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
||||
(zero_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
||||
""
|
||||
"%0 = %d1 * %h2, %3 = %h1 * %d2 (IS,M)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "usmulhisi_hl_hul"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
||||
(zero_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
||||
""
|
||||
"%0 = %d1 * %h2, %3 = %d1 * %h2 (IS,M)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "usmulhisi_hl_huh"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 0)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
||||
(zero_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
||||
""
|
||||
"%0 = %d1 * %h2, %3 = %d1 * %d2 (IS,M)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "usmulhisi_hh_lul"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
||||
(zero_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
||||
""
|
||||
"%0 = %d1 * %d2, %3 = %h1 * %h2 (IS,M)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "usmulhisi_hh_luh"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
||||
(zero_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
||||
""
|
||||
"%0 = %d1 * %d2, %3 = %h1 * %d2 (IS,M)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "usmulhisi_hh_hul"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
||||
(zero_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
||||
""
|
||||
"%0 = %d1 * %d2, %3 = %d1 * %h2 (IS,M)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "usmulhisi_hh_huh"
|
||||
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
||||
(parallel [(const_int 1)])))))
|
||||
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
||||
(mult:SI (sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
||||
(zero_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
||||
""
|
||||
"%0 = %d1 * %d2, %3 = %d1 * %d2 (IS,M)%!"
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
;; Vector neg/abs.
|
||||
|
||||
(define_insn "ssnegv2hi2"
|
||||
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
||||
(ss_neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user