reorg.c: Remove an obsolete comment.
* reorg.c: Remove an obsolete comment. * config/pa/pa.md: Add back the HP-PA comment here, with details. From-SVN: r194039
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2012-12-02 Steven Bosscher <steven@gcc.gnu.org>
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* reorg.c: Remove an obsolete comment.
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* config/pa/pa.md: Add back the HP-PA comment here, with details.
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2012-11-30 Eric Botcazou <ebotcazou@adacore.com>
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* stor-layout.c (bit_field_mode_iterator::bit_field_mode_iterator): Deal
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@ -1,6 +1,5 @@
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;;- Machine description for HP PA-RISC architecture for GCC compiler
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;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
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;; 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
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;; Copyright (C) 1992-2012
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;; Free Software Foundation, Inc.
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;; Contributed by the Center for Software Science at the University
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;; of Utah.
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@ -21,8 +20,52 @@
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; This gcc Version 2 machine description is inspired by sparc.md and
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;; mips.md.
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;; This machine description is inspired by sparc.md and to a lesser
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;; extent mips.md.
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;; Possible improvements:
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;;
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;; * With PA1.1, most computational instructions can conditionally nullify
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;; the execution of the following instruction. A nullified instruction
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;; does not cause the instruction pipeline to stall, making it a very
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;; efficient alternative to e.g. branching or conditional moves.
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;;
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;; Nullification is performed conditionally based on the outcome of a
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;; test specified in the opcode. The test result is stored in PSW[N]
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;; and can only be used to nullify the instruction following immediately
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;; after the test. For example:
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;;
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;; ldi 10,%r26
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;; ldi 5,%r25
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;; sub,< %r26,%r25,%r28
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;; sub %r28,%r25,%r28 ; %r28 == 0
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;; sub,> %r26,%r25,%r29
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;; sub %r29,%r25,%r29 ; %r29 == 5
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;;
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;; This could be tricky to implement because the result of the test has
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;; to be propagated one instruction forward, which, in the worst case,
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;; would involve (1) adding a fake register for PSW[N]; (2) adding the
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;; variants of the computational instructions that set or consume this
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;; fake register. The cond_exec infrastructure is probably not helpful
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;; for this.
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;;
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;; * PA-RISC includes a set of conventions for branch instruction usage
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;; to indicate whether a particular branch is more likely to be taken
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;; or not taken. For example, the prediction for CMPB instructions
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;; (CMPB,cond,n r1,r2,target) depends on the direction of the branch
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;; (forward or backward) and on the order of the operands:
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;;
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;; | branch | operand | branch |
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;; | direction | compare | prediction |
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;; +-----------+----------+------------+
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;; | backward | r1 < r2 | taken |
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;; | backward | r1 >= r2 | not taken |
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;; | forward | r1 < r2 | not taken |
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;; | forward | r1 >= r2 | taken |
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;;
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;; By choosing instructions and operand order carefully, the compiler
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;; could give the CPU branch predictor some help.
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;;
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;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
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11
gcc/reorg.c
11
gcc/reorg.c
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@ -100,16 +100,7 @@ along with GCC; see the file COPYING3. If not see
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delay slot. In that case, we point each insn at the other with REG_CC_USER
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and REG_CC_SETTER notes. Note that these restrictions affect very few
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machines because most RISC machines with delay slots will not use CC0
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(the RT is the only known exception at this point).
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Not yet implemented:
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The Acorn Risc Machine can conditionally execute most insns, so
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it is profitable to move single insns into a position to execute
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based on the condition code of the previous insn.
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The HP-PA can conditionally nullify insns, providing a similar
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effect to the ARM, differing mostly in which insn is "in charge". */
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(the RT is the only known exception at this point). */
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#include "config.h"
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#include "system.h"
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