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Some SSE fixes 

From-SVN: r47096
This commit is contained in:
Bernd Schmidt 2001-11-16 19:58:40 +00:00 committed by Bernd Schmidt
parent 54b6b24152
commit 29628f27db
3 changed files with 48 additions and 18 deletions
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12
gcc/ChangeLog
View File

@ -1,3 +1,15 @@
2001-11-16 Bernd Schmidt <bernds@redhat.com>
* config/i386/i386.c (ix86_expand_sse_comi): Generate setcc by
hand; don't use gen_setcc_2.
(ix86_expand_builtin): Fix pshufw.
* config/i386/i386.md (maskncmpv4sf3, vmmmaskncmpv4sf3): Special
case UNORDERED to emit the right assembler instruction.
(mmx_pshufw): Lose operand 2.
(cvtsi2ss): Fix representation.
From Graham Stott:
(mmx_clrdi, sse_clrti, stmxcsr, ldmxcsr): Set memory attribute.
2001-11-16 Joseph S. Myers <jsm28@cam.ac.uk>
* doc/include/linux-and-gnu.texi: Remove.

18
gcc/config/i386/i386.c
View File

@ -11648,7 +11648,11 @@ ix86_expand_sse_comi (d, arglist, target)
if (! pat)
return 0;
emit_insn (pat);
emit_insn (gen_setcc_2 (target, op2));
emit_insn (gen_rtx_SET (VOIDmode,
gen_rtx_STRICT_LOW_PART (VOIDmode, target),
gen_rtx_fmt_ee (comparison, QImode,
gen_rtx_REG (CCmode, FLAGS_REG),
const0_rtx)));
return target;
}
@ -11936,12 +11940,12 @@ ix86_expand_builtin (exp, target, subtarget, mode, ignore)
op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
tmode = insn_data[icode].operand[0].mode;
mode0 = insn_data[icode].operand[2].mode;
mode1 = insn_data[icode].operand[3].mode;
mode1 = insn_data[icode].operand[1].mode;
mode2 = insn_data[icode].operand[2].mode;
if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
op0 = copy_to_mode_reg (mode0, op0);
if (! (*insn_data[icode].operand[3].predicate) (op1, mode1))
if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
op0 = copy_to_mode_reg (mode1, op0);
if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
{
/* @@@ better error message */
error ("mask must be an immediate");
@ -11951,7 +11955,7 @@ ix86_expand_builtin (exp, target, subtarget, mode, ignore)
|| GET_MODE (target) != tmode
|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
target = gen_reg_rtx (tmode);
pat = GEN_FCN (icode) (target, target, op0, op1);
pat = GEN_FCN (icode) (target, op0, op1);
if (! pat)
return 0;
emit_insn (pat);

36
gcc/config/i386/i386.md
View File

@ -18454,8 +18454,8 @@
(unspec:TI [(const_int 0)] 45))]
"TARGET_SSE"
"xorps\t{%0, %0|%0, %0}"
[(set_attr "type" "sse")])
[(set_attr "type" "sse")
(set_attr "memory" "none")])
;; SSE mask-generating compares
@ -18475,7 +18475,13 @@
[(match_operand:V4SF 1 "register_operand" "0")
(match_operand:V4SF 2 "nonimmediate_operand" "x")])))]
"TARGET_SSE"
"cmpn%D3ps\t{%2, %0|%0, %2}"
"*
{
if (GET_CODE (operands[3]) == UNORDERED)
return \"cmpordps\t{%2, %0|%0, %2}\";
return \"cmpn%D3ps\t{%2, %0|%0, %2}\";
}"
[(set_attr "type" "sse")])
(define_insn "vmmaskcmpv4sf3"
@ -18500,7 +18506,13 @@
(subreg:V4SI (match_dup 1) 0)
(const_int 1)))]
"TARGET_SSE"
"cmp%D3ss\t{%2, %0|%0, %2}"
"*
{
if (GET_CODE (operands[3]) == UNORDERED)
return \"cmpordss\t{%2, %0|%0, %2}\";
return \"cmpn%D3ss\t{%2, %0|%0, %2}\";
}"
[(set_attr "type" "sse")])
(define_insn "sse_comi"
@ -18645,7 +18657,7 @@
(vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
(vec_duplicate:V4SF
(float:SF (match_operand:SI 2 "register_operand" "rm")))
(const_int 15)))]
(const_int 14)))]
"TARGET_SSE"
"cvtsi2ss\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
@ -18855,7 +18867,8 @@
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
"pxor\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")])
[(set_attr "type" "mmx")
(set_attr "memory" "none")])
;; Same as pxor, but don't show input operands so that we don't think
;; they are live.
@ -18954,10 +18967,9 @@
(define_insn "mmx_pshufw"
[(set (match_operand:V4HI 0 "register_operand" "=y")
(unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")
(match_operand:SI 3 "immediate_operand" "i")] 41))]
(match_operand:SI 2 "immediate_operand" "i")] 41))]
"TARGET_SSE || TARGET_3DNOW_A"
"pshufw\t{%3, %2, %0|%0, %2, %3}"
"pshufw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sse")])
@ -19293,14 +19305,16 @@
[(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 37)]
"TARGET_MMX"
"ldmxcsr\t%0"
[(set_attr "type" "mmx")])
[(set_attr "type" "mmx")
(set_attr "memory" "load")])
(define_insn "stmxcsr"
[(set (match_operand:SI 0 "memory_operand" "=m")
(unspec_volatile:SI [(const_int 0)] 40))]
"TARGET_MMX"
"stmxcsr\t%0"
[(set_attr "type" "mmx")])
[(set_attr "type" "mmx")
(set_attr "memory" "store")])
(define_expand "sfence"
[(set (match_dup 0)