re PR target/79812 (ICE in simplify_binary_operation_1, at simplify-rtx.c:3586)
PR target/79812 * config/i386/sse.md (VI8F_256_512): Remove mode iterator. (<avx2_avx512>_perm<mode>): Rename to ... (avx2_perm<mode>): ... this. Use VI8F_256 iterator instead of VI8F_256_512. (<avx512>_perm<mode>_mask): Rename to ... (avx512vl_perm<mode>_mask): ... this. Use VI8F_256 iterator instead of VI8F_256_512. (<avx2_avx512>_perm<mode>_1<mask_name>): Rename to ... (avx2_perm<mode>_1<mask_name): ... this. Use VI8F_256 iterator instead of VI8F_256_512. (avx512f_perm<mode>): New define_expand. (avx512f_perm<mode>_mask): Likewise. (avx512f_perm<mode>_1<mask_name>): New define_insn. (<avx512>_vec_dup<mode>_1): Fix up vec_select mode. * gcc.target/i386/avx512f-vpermq-imm-3.c: New test. From-SVN: r245915
This commit is contained in:
Jakub Jelinek
Jakub Jelinek
parent
ca8942a34a
commit
296cc393ef
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@ -1,3 +1,21 @@
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2017-03-06 Jakub Jelinek <jakub@redhat.com>
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PR target/79812
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* config/i386/sse.md (VI8F_256_512): Remove mode iterator.
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(<avx2_avx512>_perm<mode>): Rename to ...
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(avx2_perm<mode>): ... this. Use VI8F_256 iterator instead
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of VI8F_256_512.
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(<avx512>_perm<mode>_mask): Rename to ...
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(avx512vl_perm<mode>_mask): ... this. Use VI8F_256 iterator instead
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of VI8F_256_512.
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(<avx2_avx512>_perm<mode>_1<mask_name>): Rename to ...
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(avx2_perm<mode>_1<mask_name): ... this. Use VI8F_256 iterator
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instead of VI8F_256_512.
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(avx512f_perm<mode>): New define_expand.
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(avx512f_perm<mode>_mask): Likewise.
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(avx512f_perm<mode>_1<mask_name>): New define_insn.
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(<avx512>_vec_dup<mode>_1): Fix up vec_select mode.
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2017-03-06 Prachi Godbole <prachi.godbole@imgtec.com>
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* config/mips/mips-msa.md (msa_fmax_a_<msafmt>, msa_fmin_a_<msafmt>,
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@ -549,8 +549,6 @@
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(define_mode_iterator VI8F_128 [V2DI V2DF])
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(define_mode_iterator VI4F_256 [V8SI V8SF])
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(define_mode_iterator VI8F_256 [V4DI V4DF])
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(define_mode_iterator VI8F_256_512
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[V4DI V4DF (V8DI "TARGET_AVX512F") (V8DF "TARGET_AVX512F")])
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(define_mode_iterator VI48F_256_512
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[V8SI V8SF
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(V16SI "TARGET_AVX512F") (V16SF "TARGET_AVX512F")
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@ -17306,43 +17304,43 @@
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(set_attr "prefix" "<mask_prefix2>")
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(set_attr "mode" "<sseinsnmode>")])
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(define_expand "<avx2_avx512>_perm<mode>"
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[(match_operand:VI8F_256_512 0 "register_operand")
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(match_operand:VI8F_256_512 1 "nonimmediate_operand")
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(define_expand "avx2_perm<mode>"
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[(match_operand:VI8F_256 0 "register_operand")
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(match_operand:VI8F_256 1 "nonimmediate_operand")
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(match_operand:SI 2 "const_0_to_255_operand")]
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"TARGET_AVX2"
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{
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int mask = INTVAL (operands[2]);
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emit_insn (gen_<avx2_avx512>_perm<mode>_1 (operands[0], operands[1],
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GEN_INT ((mask >> 0) & 3),
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GEN_INT ((mask >> 2) & 3),
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GEN_INT ((mask >> 4) & 3),
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GEN_INT ((mask >> 6) & 3)));
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emit_insn (gen_avx2_perm<mode>_1 (operands[0], operands[1],
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GEN_INT ((mask >> 0) & 3),
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GEN_INT ((mask >> 2) & 3),
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GEN_INT ((mask >> 4) & 3),
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GEN_INT ((mask >> 6) & 3)));
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DONE;
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})
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(define_expand "<avx512>_perm<mode>_mask"
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[(match_operand:VI8F_256_512 0 "register_operand")
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(match_operand:VI8F_256_512 1 "nonimmediate_operand")
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(define_expand "avx512vl_perm<mode>_mask"
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[(match_operand:VI8F_256 0 "register_operand")
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(match_operand:VI8F_256 1 "nonimmediate_operand")
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(match_operand:SI 2 "const_0_to_255_operand")
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(match_operand:VI8F_256_512 3 "vector_move_operand")
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(match_operand:VI8F_256 3 "vector_move_operand")
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(match_operand:<avx512fmaskmode> 4 "register_operand")]
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"TARGET_AVX512F"
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"TARGET_AVX512VL"
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{
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int mask = INTVAL (operands[2]);
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emit_insn (gen_<avx2_avx512>_perm<mode>_1_mask (operands[0], operands[1],
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GEN_INT ((mask >> 0) & 3),
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GEN_INT ((mask >> 2) & 3),
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GEN_INT ((mask >> 4) & 3),
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GEN_INT ((mask >> 6) & 3),
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operands[3], operands[4]));
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GEN_INT ((mask >> 0) & 3),
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GEN_INT ((mask >> 2) & 3),
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GEN_INT ((mask >> 4) & 3),
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GEN_INT ((mask >> 6) & 3),
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operands[3], operands[4]));
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DONE;
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})
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(define_insn "<avx2_avx512>_perm<mode>_1<mask_name>"
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[(set (match_operand:VI8F_256_512 0 "register_operand" "=v")
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(vec_select:VI8F_256_512
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(match_operand:VI8F_256_512 1 "nonimmediate_operand" "vm")
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(define_insn "avx2_perm<mode>_1<mask_name>"
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[(set (match_operand:VI8F_256 0 "register_operand" "=v")
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(vec_select:VI8F_256
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(match_operand:VI8F_256 1 "nonimmediate_operand" "vm")
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(parallel [(match_operand 2 "const_0_to_3_operand")
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(match_operand 3 "const_0_to_3_operand")
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(match_operand 4 "const_0_to_3_operand")
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@ -17361,6 +17359,77 @@
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(set_attr "prefix" "<mask_prefix2>")
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(set_attr "mode" "<sseinsnmode>")])
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(define_expand "avx512f_perm<mode>"
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[(match_operand:V8FI 0 "register_operand")
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(match_operand:V8FI 1 "nonimmediate_operand")
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(match_operand:SI 2 "const_0_to_255_operand")]
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"TARGET_AVX512F"
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{
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int mask = INTVAL (operands[2]);
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emit_insn (gen_avx512f_perm<mode>_1 (operands[0], operands[1],
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GEN_INT ((mask >> 0) & 3),
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GEN_INT ((mask >> 2) & 3),
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GEN_INT ((mask >> 4) & 3),
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GEN_INT ((mask >> 6) & 3),
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GEN_INT (((mask >> 0) & 3) + 4),
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GEN_INT (((mask >> 2) & 3) + 4),
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GEN_INT (((mask >> 4) & 3) + 4),
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GEN_INT (((mask >> 6) & 3) + 4)));
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DONE;
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})
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(define_expand "avx512f_perm<mode>_mask"
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[(match_operand:V8FI 0 "register_operand")
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(match_operand:V8FI 1 "nonimmediate_operand")
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(match_operand:SI 2 "const_0_to_255_operand")
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(match_operand:V8FI 3 "vector_move_operand")
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(match_operand:<avx512fmaskmode> 4 "register_operand")]
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"TARGET_AVX512F"
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{
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int mask = INTVAL (operands[2]);
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emit_insn (gen_avx512f_perm<mode>_1_mask (operands[0], operands[1],
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GEN_INT ((mask >> 0) & 3),
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GEN_INT ((mask >> 2) & 3),
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GEN_INT ((mask >> 4) & 3),
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GEN_INT ((mask >> 6) & 3),
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GEN_INT (((mask >> 0) & 3) + 4),
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GEN_INT (((mask >> 2) & 3) + 4),
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GEN_INT (((mask >> 4) & 3) + 4),
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GEN_INT (((mask >> 6) & 3) + 4),
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operands[3], operands[4]));
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DONE;
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})
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(define_insn "avx512f_perm<mode>_1<mask_name>"
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[(set (match_operand:V8FI 0 "register_operand" "=v")
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(vec_select:V8FI
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(match_operand:V8FI 1 "nonimmediate_operand" "vm")
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(parallel [(match_operand 2 "const_0_to_3_operand")
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(match_operand 3 "const_0_to_3_operand")
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(match_operand 4 "const_0_to_3_operand")
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(match_operand 5 "const_0_to_3_operand")
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(match_operand 6 "const_4_to_7_operand")
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(match_operand 7 "const_4_to_7_operand")
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(match_operand 8 "const_4_to_7_operand")
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(match_operand 9 "const_4_to_7_operand")])))]
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"TARGET_AVX512F && <mask_mode512bit_condition>
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&& (INTVAL (operands[2]) == (INTVAL (operands[6]) - 4)
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&& INTVAL (operands[3]) == (INTVAL (operands[7]) - 4)
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&& INTVAL (operands[4]) == (INTVAL (operands[8]) - 4)
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&& INTVAL (operands[5]) == (INTVAL (operands[9]) - 4))"
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{
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int mask = 0;
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mask |= INTVAL (operands[2]) << 0;
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mask |= INTVAL (operands[3]) << 2;
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mask |= INTVAL (operands[4]) << 4;
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mask |= INTVAL (operands[5]) << 6;
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operands[2] = GEN_INT (mask);
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return "vperm<ssemodesuffix>\t{%2, %1, %0<mask_operand10>|%0<mask_operand10>, %1, %2}";
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}
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[(set_attr "type" "sselog")
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(set_attr "prefix" "<mask_prefix2>")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "avx2_permv2ti"
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[(set (match_operand:V4DI 0 "register_operand" "=x")
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(unspec:V4DI
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@ -17389,7 +17458,7 @@
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(define_insn "<avx512>_vec_dup<mode>_1"
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[(set (match_operand:VI_AVX512BW 0 "register_operand" "=v,v")
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(vec_duplicate:VI_AVX512BW
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(vec_select:VI_AVX512BW
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(vec_select:<ssescalarmode>
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(match_operand:VI_AVX512BW 1 "nonimmediate_operand" "v,m")
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(parallel [(const_int 0)]))))]
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"TARGET_AVX512F"
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@ -1,3 +1,8 @@
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2017-03-06 Jakub Jelinek <jakub@redhat.com>
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PR target/79812
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* gcc.target/i386/avx512f-vpermq-imm-3.c: New test.
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2017-03-06 Toma Tabacu <toma.tabacu@imgtec.com>
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* gcc.target/mips/inline-memcpy-3.c (dg-options): Add -mabi=32.
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@ -0,0 +1,5 @@
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/* PR target/79812 */
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/* { dg-do compile } */
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/* { dg-options "-O3 -mavx512f" } */
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#include "avx512f-vpermq-imm-2.c"
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