aarch64.md (*and<mode>3_compare0): New pattern.
2013-03-28 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com> * config/aarch64/aarch64.md (*and<mode>3_compare0): New pattern. (*andsi3_compare0_uxtw): New pattern. (*and_<SHIFT:optab><mode>3_compare0): New pattern. (*and_<SHIFT:optab>si3_compare0_uxtw): New pattern. From-SVN: r197207
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2013-03-28 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
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* config/aarch64/aarch64.md (*and<mode>3_compare0): New pattern.
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(*andsi3_compare0_uxtw): New pattern.
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(*and_<SHIFT:optab><mode>3_compare0): New pattern.
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(*and_<SHIFT:optab>si3_compare0_uxtw): New pattern.
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2013-03-28 Jan Hubicka <jh@suse.cz>
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2013-03-28 Jan Hubicka <jh@suse.cz>
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* data-streamer-in.c (streamer_read_gcov_count): New function.
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* data-streamer-in.c (streamer_read_gcov_count): New function.
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@ -2461,6 +2461,69 @@
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[(set_attr "v8type" "logic,logic_imm")
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[(set_attr "v8type" "logic,logic_imm")
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(set_attr "mode" "SI")])
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(set_attr "mode" "SI")])
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(define_insn "*and<mode>3_compare0"
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[(set (reg:CC_NZ CC_REGNUM)
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(compare:CC_NZ
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(and:GPI (match_operand:GPI 1 "register_operand" "%r,r")
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(match_operand:GPI 2 "aarch64_logical_operand" "r,<lconst>"))
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(const_int 0)))
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(set (match_operand:GPI 0 "register_operand" "=r,r")
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(and:GPI (match_dup 1) (match_dup 2)))]
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""
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"ands\\t%<w>0, %<w>1, %<w>2"
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[(set_attr "v8type" "logics,logics_imm")
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(set_attr "mode" "<MODE>")]
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)
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;; zero_extend version of above
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(define_insn "*andsi3_compare0_uxtw"
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[(set (reg:CC_NZ CC_REGNUM)
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(compare:CC_NZ
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(and:SI (match_operand:SI 1 "register_operand" "%r,r")
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(match_operand:SI 2 "aarch64_logical_operand" "r,K"))
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(const_int 0)))
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(set (match_operand:DI 0 "register_operand" "=r,r")
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(zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
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""
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"ands\\t%w0, %w1, %w2"
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[(set_attr "v8type" "logics,logics_imm")
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(set_attr "mode" "SI")]
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)
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(define_insn "*and_<SHIFT:optab><mode>3_compare0"
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[(set (reg:CC_NZ CC_REGNUM)
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(compare:CC_NZ
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(and:GPI (SHIFT:GPI
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(match_operand:GPI 1 "register_operand" "r")
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(match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))
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(match_operand:GPI 3 "register_operand" "r"))
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(const_int 0)))
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(set (match_operand:GPI 0 "register_operand" "=r")
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(and:GPI (SHIFT:GPI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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""
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"ands\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2"
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[(set_attr "v8type" "logics_shift")
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(set_attr "mode" "<MODE>")]
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)
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;; zero_extend version of above
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(define_insn "*and_<SHIFT:optab>si3_compare0_uxtw"
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[(set (reg:CC_NZ CC_REGNUM)
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(compare:CC_NZ
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(and:SI (SHIFT:SI
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(match_operand:SI 1 "register_operand" "r")
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(match_operand:QI 2 "aarch64_shift_imm_si" "n"))
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(match_operand:SI 3 "register_operand" "r"))
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(const_int 0)))
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(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI (and:SI (SHIFT:SI (match_dup 1) (match_dup 2))
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(match_dup 3))))]
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""
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"ands\\t%w0, %w3, %w1, <SHIFT:shift> %2"
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[(set_attr "v8type" "logics_shift")
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(set_attr "mode" "SI")]
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)
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(define_insn "*<LOGICAL:optab>_<SHIFT:optab><mode>3"
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(define_insn "*<LOGICAL:optab>_<SHIFT:optab><mode>3"
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[(set (match_operand:GPI 0 "register_operand" "=r")
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[(set (match_operand:GPI 0 "register_operand" "=r")
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(LOGICAL:GPI (SHIFT:GPI
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(LOGICAL:GPI (SHIFT:GPI
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