xtensa-config.h (XCHAL_HAVE_THREADPTR): New.
include/ * xtensa-config.h (XCHAL_HAVE_THREADPTR): New. (XCHAL_HAVE_RELEASE_SYNC, XCHAL_HAVE_S32C1I): New. gcc/ * config/xtensa/xtensa.c (xtensa_expand_mask_and_shift): New. (struct alignment_context, init_alignment_context): New. (xtensa_expand_compare_and_swap, xtensa_expand_atomic): New. * config/xtensa/xtensa.h (XCHAL_HAVE_RELEASE_SYNC): Add default. (XCHAL_HAVE_S32C1I): Likewise. (TARGET_RELEASE_SYNC, TARGET_S32C1I): New. * config/xtensa/xtensa.md (UNSPECV_MEMW): New constant. (UNSPECV_S32RI, UNSPECV_S32C1I): Likewise. (ATOMIC, HQI): New macros. (memory_barrier, *memory_barrier): New. (sync_lock_releasesi): New. (sync_compare_and_swapsi, sync_compare_and_swap<mode>): New. (sync_lock_test_and_set<mode>): New. (sync_<atomic><mode>): New. (sync_old_<atomic><mode>, sync_new_<atomic><mode>): New. * config/xtensa/xtensa-protos.h (xtensa_expand_compare_and_swap): New. (xtensa_expand_atomic): New. gcc/testsuite/ * lib/target-supports.exp (check_effective_target_sync_int_long): Enable for xtensa. (check_effective_target_sync_char_short): Likewise. From-SVN: r126728
This commit is contained in:
Bob Wilson
Bob Wilson
parent
8a91c45bbf
commit
2a48b790b2
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@ -1,3 +1,23 @@
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2007-07-18 Bob Wilson <bob.wilson@acm.org>
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* config/xtensa/xtensa.c (xtensa_expand_mask_and_shift): New.
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(struct alignment_context, init_alignment_context): New.
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(xtensa_expand_compare_and_swap, xtensa_expand_atomic): New.
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* config/xtensa/xtensa.h (XCHAL_HAVE_RELEASE_SYNC): Add default.
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(XCHAL_HAVE_S32C1I): Likewise.
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(TARGET_RELEASE_SYNC, TARGET_S32C1I): New.
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* config/xtensa/xtensa.md (UNSPECV_MEMW): New constant.
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(UNSPECV_S32RI, UNSPECV_S32C1I): Likewise.
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(ATOMIC, HQI): New macros.
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(memory_barrier, *memory_barrier): New.
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(sync_lock_releasesi): New.
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(sync_compare_and_swapsi, sync_compare_and_swap<mode>): New.
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(sync_lock_test_and_set<mode>): New.
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(sync_<atomic><mode>): New.
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(sync_old_<atomic><mode>, sync_new_<atomic><mode>): New.
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* config/xtensa/xtensa-protos.h (xtensa_expand_compare_and_swap): New.
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(xtensa_expand_atomic): New.
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2007-07-18 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
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PR target/30652
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@ -47,6 +47,8 @@ extern void xtensa_split_operand_pair (rtx *, enum machine_mode);
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extern int xtensa_emit_move_sequence (rtx *, enum machine_mode);
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extern rtx xtensa_copy_incoming_a7 (rtx);
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extern void xtensa_expand_nonlocal_goto (rtx *);
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extern void xtensa_expand_compare_and_swap (rtx, rtx, rtx, rtx);
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extern void xtensa_expand_atomic (enum rtx_code, rtx, rtx, rtx, bool);
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extern void xtensa_emit_loop_end (rtx, rtx *);
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extern char *xtensa_emit_branch (bool, bool, rtx *);
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extern char *xtensa_emit_bit_branch (bool, bool, rtx *);
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@ -1198,6 +1198,263 @@ xtensa_init_machine_status (void)
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}
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/* Shift VAL of mode MODE left by COUNT bits. */
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static inline rtx
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xtensa_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
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{
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val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
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NULL_RTX, 1, OPTAB_DIRECT);
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return expand_simple_binop (SImode, ASHIFT, val, count,
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NULL_RTX, 1, OPTAB_DIRECT);
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}
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/* Structure to hold the initial parameters for a compare_and_swap operation
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in HImode and QImode. */
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struct alignment_context
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{
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rtx memsi; /* SI aligned memory location. */
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rtx shift; /* Bit offset with regard to lsb. */
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rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
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rtx modemaski; /* ~modemask */
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};
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/* Initialize structure AC for word access to HI and QI mode memory. */
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static void
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init_alignment_context (struct alignment_context *ac, rtx mem)
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{
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enum machine_mode mode = GET_MODE (mem);
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rtx byteoffset = NULL_RTX;
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bool aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
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if (aligned)
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ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
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else
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{
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/* Alignment is unknown. */
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rtx addr, align;
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/* Force the address into a register. */
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addr = force_reg (Pmode, XEXP (mem, 0));
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/* Align it to SImode. */
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align = expand_simple_binop (Pmode, AND, addr,
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GEN_INT (-GET_MODE_SIZE (SImode)),
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NULL_RTX, 1, OPTAB_DIRECT);
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/* Generate MEM. */
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ac->memsi = gen_rtx_MEM (SImode, align);
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MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
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set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
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set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
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byteoffset = expand_simple_binop (Pmode, AND, addr,
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GEN_INT (GET_MODE_SIZE (SImode) - 1),
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NULL_RTX, 1, OPTAB_DIRECT);
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}
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/* Calculate shiftcount. */
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if (TARGET_BIG_ENDIAN)
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{
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ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
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if (!aligned)
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ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
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NULL_RTX, 1, OPTAB_DIRECT);
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}
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else
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{
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if (aligned)
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ac->shift = NULL_RTX;
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else
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ac->shift = byteoffset;
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}
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if (ac->shift != NULL_RTX)
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{
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/* Shift is the byte count, but we need the bitcount. */
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ac->shift = expand_simple_binop (SImode, MULT, ac->shift,
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GEN_INT (BITS_PER_UNIT),
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NULL_RTX, 1, OPTAB_DIRECT);
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ac->modemask = expand_simple_binop (SImode, ASHIFT,
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GEN_INT (GET_MODE_MASK (mode)),
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ac->shift,
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NULL_RTX, 1, OPTAB_DIRECT);
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}
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else
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ac->modemask = GEN_INT (GET_MODE_MASK (mode));
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ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
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}
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/* Expand an atomic compare and swap operation for HImode and QImode.
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MEM is the memory location, CMP the old value to compare MEM with
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and NEW the value to set if CMP == MEM. */
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void
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xtensa_expand_compare_and_swap (rtx target, rtx mem, rtx cmp, rtx new)
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{
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enum machine_mode mode = GET_MODE (mem);
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struct alignment_context ac;
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rtx tmp, cmpv, newv, val;
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rtx oldval = gen_reg_rtx (SImode);
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rtx res = gen_reg_rtx (SImode);
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rtx csloop = gen_label_rtx ();
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rtx csend = gen_label_rtx ();
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init_alignment_context (&ac, mem);
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if (ac.shift != NULL_RTX)
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{
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cmp = xtensa_expand_mask_and_shift (cmp, mode, ac.shift);
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new = xtensa_expand_mask_and_shift (new, mode, ac.shift);
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}
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/* Load the surrounding word into VAL with the MEM value masked out. */
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val = force_reg (SImode, expand_simple_binop (SImode, AND, ac.memsi,
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ac.modemaski, NULL_RTX, 1,
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OPTAB_DIRECT));
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emit_label (csloop);
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/* Patch CMP and NEW into VAL at correct position. */
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cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
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NULL_RTX, 1, OPTAB_DIRECT));
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newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new, val,
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NULL_RTX, 1, OPTAB_DIRECT));
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/* Jump to end if we're done. */
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emit_insn (gen_sync_compare_and_swapsi (res, ac.memsi, cmpv, newv));
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emit_cmp_and_jump_insns (res, cmpv, EQ, const0_rtx, SImode, true, csend);
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/* Check for changes outside mode. */
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emit_move_insn (oldval, val);
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tmp = expand_simple_binop (SImode, AND, res, ac.modemaski,
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val, 1, OPTAB_DIRECT);
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if (tmp != val)
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emit_move_insn (val, tmp);
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/* Loop internal if so. */
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emit_cmp_and_jump_insns (oldval, val, NE, const0_rtx, SImode, true, csloop);
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emit_label (csend);
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/* Return the correct part of the bitfield. */
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convert_move (target,
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(ac.shift == NULL_RTX ? res
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: expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
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NULL_RTX, 1, OPTAB_DIRECT)),
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1);
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}
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/* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
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the default expansion works fine for SImode). MEM is the memory location
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and VAL the value to play with. If AFTER is true then store the value
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MEM holds after the operation, if AFTER is false then store the value MEM
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holds before the operation. If TARGET is zero then discard that value, else
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store it to TARGET. */
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void
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xtensa_expand_atomic (enum rtx_code code, rtx target, rtx mem, rtx val,
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bool after)
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{
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enum machine_mode mode = GET_MODE (mem);
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struct alignment_context ac;
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rtx csloop = gen_label_rtx ();
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rtx cmp, tmp;
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rtx old = gen_reg_rtx (SImode);
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rtx new = gen_reg_rtx (SImode);
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rtx orig = NULL_RTX;
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init_alignment_context (&ac, mem);
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/* Prepare values before the compare-and-swap loop. */
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if (ac.shift != NULL_RTX)
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val = xtensa_expand_mask_and_shift (val, mode, ac.shift);
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switch (code)
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{
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case PLUS:
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case MINUS:
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orig = gen_reg_rtx (SImode);
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convert_move (orig, val, 1);
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break;
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case SET:
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case IOR:
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case XOR:
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break;
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case MULT: /* NAND */
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case AND:
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/* val = "11..1<val>11..1" */
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val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
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NULL_RTX, 1, OPTAB_DIRECT);
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break;
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default:
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gcc_unreachable ();
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}
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/* Load full word. Subsequent loads are performed by S32C1I. */
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cmp = force_reg (SImode, ac.memsi);
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emit_label (csloop);
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emit_move_insn (old, cmp);
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switch (code)
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{
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case PLUS:
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case MINUS:
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val = expand_simple_binop (SImode, code, old, orig,
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NULL_RTX, 1, OPTAB_DIRECT);
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val = expand_simple_binop (SImode, AND, val, ac.modemask,
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NULL_RTX, 1, OPTAB_DIRECT);
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/* FALLTHRU */
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case SET:
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tmp = expand_simple_binop (SImode, AND, old, ac.modemaski,
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NULL_RTX, 1, OPTAB_DIRECT);
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tmp = expand_simple_binop (SImode, IOR, tmp, val,
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new, 1, OPTAB_DIRECT);
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break;
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case AND:
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case IOR:
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case XOR:
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tmp = expand_simple_binop (SImode, code, old, val,
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new, 1, OPTAB_DIRECT);
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break;
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case MULT: /* NAND */
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tmp = expand_simple_binop (SImode, XOR, old, ac.modemask,
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NULL_RTX, 1, OPTAB_DIRECT);
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tmp = expand_simple_binop (SImode, AND, tmp, val,
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new, 1, OPTAB_DIRECT);
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break;
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default:
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gcc_unreachable ();
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}
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if (tmp != new)
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emit_move_insn (new, tmp);
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emit_insn (gen_sync_compare_and_swapsi (cmp, ac.memsi, old, new));
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emit_cmp_and_jump_insns (cmp, old, NE, const0_rtx, SImode, true, csloop);
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if (target)
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{
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tmp = (after ? new : cmp);
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convert_move (target,
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(ac.shift == NULL_RTX ? tmp
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: expand_simple_binop (SImode, LSHIFTRT, tmp, ac.shift,
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NULL_RTX, 1, OPTAB_DIRECT)),
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1);
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}
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}
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void
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xtensa_setup_frame_addresses (void)
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{
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@ -47,6 +47,12 @@ extern unsigned xtensa_current_frame_size;
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#ifndef XCHAL_HAVE_MUL32_HIGH
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#define XCHAL_HAVE_MUL32_HIGH 0
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#endif
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#ifndef XCHAL_HAVE_RELEASE_SYNC
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#define XCHAL_HAVE_RELEASE_SYNC 0
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#endif
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#ifndef XCHAL_HAVE_S32C1I
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#define XCHAL_HAVE_S32C1I 0
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#endif
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#define TARGET_BIG_ENDIAN XCHAL_HAVE_BE
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#define TARGET_DENSITY XCHAL_HAVE_DENSITY
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#define TARGET_MAC16 XCHAL_HAVE_MAC16
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|
|
@ -65,6 +71,8 @@ extern unsigned xtensa_current_frame_size;
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#define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT
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#define TARGET_ABS XCHAL_HAVE_ABS
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#define TARGET_ADDX XCHAL_HAVE_ADDX
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#define TARGET_RELEASE_SYNC XCHAL_HAVE_RELEASE_SYNC
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#define TARGET_S32C1I XCHAL_HAVE_S32C1I
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#define TARGET_DEFAULT ( \
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(XCHAL_HAVE_L32R ? 0 : MASK_CONST16))
|
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|
|
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|
|
@ -30,8 +30,12 @@
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(UNSPEC_NOP 2)
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(UNSPEC_PLT 3)
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(UNSPEC_RET_ADDR 4)
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|
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(UNSPECV_SET_FP 1)
|
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(UNSPECV_ENTRY 2)
|
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(UNSPECV_MEMW 3)
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(UNSPECV_S32RI 4)
|
||||
(UNSPECV_S32C1I 5)
|
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])
|
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|
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;; This code macro allows signed and unsigned widening multiplications
|
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|
|
@ -63,6 +67,15 @@
|
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;; This code macro is for floating-point comparisons.
|
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(define_code_macro any_scc_sf [eq lt le])
|
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|
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;; These macros allow to combine most atomic operations.
|
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(define_code_macro ATOMIC [and ior xor plus minus mult])
|
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(define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
|
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(plus "add") (minus "sub") (mult "nand")])
|
||||
|
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;; These mode macros allow the HI and QI patterns to be defined from
|
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;; the same template.
|
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(define_mode_macro HQI [HI QI])
|
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|
||||
|
||||
;; Attributes.
|
||||
|
||||
|
|
@ -1687,3 +1700,113 @@ srli\t%3, %3, 30\;slli\t%0, %1, 2\;ssai\t2\;src\t%0, %3, %0"
|
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[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")
|
||||
(set_attr "length" "3")])
|
||||
|
||||
|
||||
;; Atomic operations
|
||||
|
||||
(define_expand "memory_barrier"
|
||||
[(set (mem:BLK (match_dup 0))
|
||||
(unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MEMW))]
|
||||
""
|
||||
{
|
||||
operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (SImode));
|
||||
MEM_VOLATILE_P (operands[0]) = 1;
|
||||
})
|
||||
|
||||
(define_insn "*memory_barrier"
|
||||
[(set (match_operand:BLK 0 "" "")
|
||||
(unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MEMW))]
|
||||
""
|
||||
"memw"
|
||||
[(set_attr "type" "unknown")
|
||||
(set_attr "mode" "none")
|
||||
(set_attr "length" "3")])
|
||||
|
||||
;; sync_lock_release is only implemented for SImode.
|
||||
;; For other modes, just use the default of a store with a memory_barrier.
|
||||
(define_insn "sync_lock_releasesi"
|
||||
[(set (match_operand:SI 0 "mem_operand" "=U")
|
||||
(unspec_volatile:SI
|
||||
[(match_operand:SI 1 "register_operand" "r")]
|
||||
UNSPECV_S32RI))]
|
||||
"TARGET_RELEASE_SYNC"
|
||||
"s32ri\t%1, %0"
|
||||
[(set_attr "type" "store")
|
||||
(set_attr "mode" "SI")
|
||||
(set_attr "length" "3")])
|
||||
|
||||
(define_insn "sync_compare_and_swapsi"
|
||||
[(parallel
|
||||
[(set (match_operand:SI 0 "register_operand" "=a")
|
||||
(match_operand:SI 1 "mem_operand" "+U"))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:SI
|
||||
[(match_dup 1)
|
||||
(match_operand:SI 2 "register_operand" "r")
|
||||
(match_operand:SI 3 "register_operand" "0")]
|
||||
UNSPECV_S32C1I))])]
|
||||
"TARGET_S32C1I"
|
||||
"wsr\t%2, SCOMPARE1\;s32c1i\t%3, %1"
|
||||
[(set_attr "type" "multi")
|
||||
(set_attr "mode" "SI")
|
||||
(set_attr "length" "6")])
|
||||
|
||||
(define_expand "sync_compare_and_swap<mode>"
|
||||
[(parallel
|
||||
[(set (match_operand:HQI 0 "register_operand" "")
|
||||
(match_operand:HQI 1 "mem_operand" ""))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:HQI
|
||||
[(match_dup 1)
|
||||
(match_operand:HQI 2 "register_operand" "")
|
||||
(match_operand:HQI 3 "register_operand" "")]
|
||||
UNSPECV_S32C1I))])]
|
||||
"TARGET_S32C1I"
|
||||
{
|
||||
xtensa_expand_compare_and_swap (operands[0], operands[1],
|
||||
operands[2], operands[3]);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "sync_lock_test_and_set<mode>"
|
||||
[(match_operand:HQI 0 "register_operand")
|
||||
(match_operand:HQI 1 "memory_operand")
|
||||
(match_operand:HQI 2 "register_operand")]
|
||||
"TARGET_S32C1I"
|
||||
{
|
||||
xtensa_expand_atomic (SET, operands[0], operands[1], operands[2], false);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "sync_<atomic><mode>"
|
||||
[(set (match_operand:HQI 0 "memory_operand")
|
||||
(ATOMIC:HQI (match_dup 0)
|
||||
(match_operand:HQI 1 "register_operand")))]
|
||||
"TARGET_S32C1I"
|
||||
{
|
||||
xtensa_expand_atomic (<CODE>, NULL_RTX, operands[0], operands[1], false);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "sync_old_<atomic><mode>"
|
||||
[(set (match_operand:HQI 0 "register_operand")
|
||||
(match_operand:HQI 1 "memory_operand"))
|
||||
(set (match_dup 1)
|
||||
(ATOMIC:HQI (match_dup 1)
|
||||
(match_operand:HQI 2 "register_operand")))]
|
||||
"TARGET_S32C1I"
|
||||
{
|
||||
xtensa_expand_atomic (<CODE>, operands[0], operands[1], operands[2], false);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "sync_new_<atomic><mode>"
|
||||
[(set (match_operand:HQI 0 "register_operand")
|
||||
(ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
|
||||
(match_operand:HQI 2 "register_operand")))
|
||||
(set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_S32C1I"
|
||||
{
|
||||
xtensa_expand_atomic (<CODE>, operands[0], operands[1], operands[2], true);
|
||||
DONE;
|
||||
})
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2007-07-18 Bob Wilson <bob.wilson@acm.org>
|
||||
|
||||
* lib/target-supports.exp (check_effective_target_sync_int_long):
|
||||
Enable for xtensa.
|
||||
(check_effective_target_sync_char_short): Likewise.
|
||||
|
||||
2007-07-18 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
|
||||
|
||||
* gcc.dg/pr28796-2.c: Add more cases.
|
||||
|
|
|
|||
|
|
@ -2188,7 +2188,8 @@ proc check_effective_target_sync_int_long { } {
|
|||
|| [istarget s390*-*-*]
|
||||
|| [istarget powerpc*-*-*]
|
||||
|| [istarget sparc64-*-*]
|
||||
|| [istarget sparcv9-*-*] } {
|
||||
|| [istarget sparcv9-*-*]
|
||||
|| [istarget xtensa-*-*] } {
|
||||
set et_sync_int_long_saved 1
|
||||
}
|
||||
}
|
||||
|
|
@ -2215,7 +2216,8 @@ proc check_effective_target_sync_char_short { } {
|
|||
|| [istarget s390*-*-*]
|
||||
|| [istarget powerpc*-*-*]
|
||||
|| [istarget sparc64-*-*]
|
||||
|| [istarget sparcv9-*-*] } {
|
||||
|| [istarget sparcv9-*-*]
|
||||
|| [istarget xtensa-*-*] } {
|
||||
set et_sync_char_short_saved 1
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2007-07-18 Bob Wilson <bob.wilson@acm.org>
|
||||
|
||||
* xtensa-config.h (XCHAL_HAVE_THREADPTR): New.
|
||||
(XCHAL_HAVE_RELEASE_SYNC, XCHAL_HAVE_S32C1I): New.
|
||||
|
||||
2007-07-17 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* COPYING3: New file. Contains version 3 of the GNU General
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* Xtensa configuration settings.
|
||||
Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006
|
||||
Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
|
||||
|
||||
|
|
@ -73,6 +73,15 @@
|
|||
#undef XCHAL_HAVE_LOOPS
|
||||
#define XCHAL_HAVE_LOOPS 1
|
||||
|
||||
#undef XCHAL_HAVE_THREADPTR
|
||||
#define XCHAL_HAVE_THREADPTR 1
|
||||
|
||||
#undef XCHAL_HAVE_RELEASE_SYNC
|
||||
#define XCHAL_HAVE_RELEASE_SYNC 0
|
||||
|
||||
#undef XCHAL_HAVE_S32C1I
|
||||
#define XCHAL_HAVE_S32C1I 0
|
||||
|
||||
#undef XCHAL_HAVE_BOOLEANS
|
||||
#define XCHAL_HAVE_BOOLEANS 0
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue