mips.c (mips_use_dfa_pipeline_interface): Add R3000.
2004-06-23 Eric Christopher <echristo@redhat.com> * config/mips/mips.c (mips_use_dfa_pipeline_interface): Add R3000. * config/mips/mips.md: Remove R3000 scheduling description. * config/mips/3000.md: New file. From-SVN: r83575
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2004-06-23 Eric Christopher <echristo@redhat.com>
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* config/mips/mips.c (mips_use_dfa_pipeline_interface): Add R3000.
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* config/mips/mips.md: Remove R3000 scheduling description.
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* config/mips/3000.md: New file.
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2004-06-23 Ulrich Weigand <uweigand@de.ibm.com>
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* config/s390/s390-protos.h (s390_emit_compare): Add prototype.
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@ -20,7 +26,7 @@
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("doloop"): Adapt.
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("jump"): Convert to expander. Use s390_emit_jump.
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("*jump_64", "*jump_31"): New insns. Improve length default.
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2004-06-23 Wu Yongwei <adah@sh163.net>
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* gthr-win32.h (__GTHREAD_MUTEX_INIT_DEFAULT): Adjust.
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69
gcc/config/mips/3000.md
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69
gcc/config/mips/3000.md
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;; DFA based pipeline description for the r3000
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;; This is a special pipeline - this is also the default schedule and
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;; so we need to schedule instructions that may not exist on the r2k/r3k.
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;; Generic processor description that assumes that the only latencies are for
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;; hazards or delay slots, otherwise everything is assumed to issue and execute
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;; in one cycle.
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(define_automaton "r3k")
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(define_cpu_unit "r3k_alu" "r3k")
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(define_insn_reservation "r3k_generic_alu" 1
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(and (eq_attr "cpu" "r3000")
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(eq_attr "type" "unknown,prefetch,prefetchx,condmove,mthilo,const,arith,shift,slt,clz,trap,fmove,fadd,fmadd,fabs,fneg,fcvt,fsqrt,frsqrt,multi,nop"))
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"r3k_alu")
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(define_insn_reservation "r3k_load_alu" 2
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(and (eq_attr "cpu" "r3000")
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(eq_attr "type" "load, fpload, fpidxload, xfer"))
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"r3k_alu*2")
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(define_insn_reservation "r3k_call_alu" 2
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(and (eq_attr "cpu" "r3000")
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(eq_attr "type" "branch,jump,call"))
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"r3k_alu*2")
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(define_insn_reservation "r3k_hilo_alu" 3
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(and (eq_attr "cpu" "r3000")
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(eq_attr "type" "mfhilo"))
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"r3k_alu*3")
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(define_insn_reservation "r3k_fcmp_alu" 2
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(and (eq_attr "cpu" "r3000")
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(eq_attr "type" "fcmp, fadd"))
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"r3k_alu*2")
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(define_insn_reservation "r3k_imul_alu" 12
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(and (eq_attr "cpu" "r3000")
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(eq_attr "type" "imul, imadd"))
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"r3k_alu*12")
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(define_insn_reservation "r3k_idiv_alu" 35
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(and (eq_attr "cpu" "r3000")
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(eq_attr "type" "idiv"))
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"r3k_alu*35")
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(define_insn_reservation "r3k_fmul_single_alu" 4
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(and (eq_attr "cpu" "r3000")
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(and (eq_attr "type" "fmul")
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(eq_attr "mode" "SF")))
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"r3k_alu*4")
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(define_insn_reservation "r3k_fmul_double_alu" 5
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(and (eq_attr "cpu" "r3000")
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(and (eq_attr "type" "fmul")
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(eq_attr "mode" "DF")))
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"r3k_alu*5")
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(define_insn_reservation "r3k_fdiv_single_alu" 12
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(and (eq_attr "cpu" "r3000")
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(and (eq_attr "type" "fdiv")
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(eq_attr "mode" "SF")))
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"r3k_alu*12")
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(define_insn_reservation "r3k_fdiv_double_alu" 19
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(and (eq_attr "cpu" "r3000")
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(and (eq_attr "type" "fdiv")
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(eq_attr "mode" "DF")))
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"r3k_alu*19")
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@ -9930,6 +9930,7 @@ mips_use_dfa_pipeline_interface (void)
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{
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switch (mips_tune)
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{
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case PROCESSOR_R3000:
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case PROCESSOR_R4130:
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case PROCESSOR_R5400:
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case PROCESSOR_R5500:
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@ -326,12 +326,12 @@
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(define_function_unit "memory" 1 0
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(and (eq_attr "type" "load,fpload,fpidxload")
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(eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
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(eq_attr "cpu" "r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
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3 0)
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(define_function_unit "memory" 1 0
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(and (eq_attr "type" "load,fpload,fpidxload")
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(eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
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(eq_attr "cpu" "r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
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2 0)
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(define_function_unit "memory" 1 0
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@ -346,7 +346,7 @@
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "imul,imadd")
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(eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
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(eq_attr "cpu" "r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
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17 17)
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;; On them mips16, we want to stronly discourage a mult from appearing
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@ -360,7 +360,7 @@
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1 5)
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r3000,r3900"))
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(and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r3900"))
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12 12)
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(define_function_unit "imuldiv" 1 0
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@ -398,11 +398,11 @@
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
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(eq_attr "cpu" "r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
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38 38)
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "idiv") (eq_attr "cpu" "r3000,r3900"))
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(and (eq_attr "type" "idiv") (eq_attr "cpu" "r3900"))
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35 35)
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(define_function_unit "imuldiv" 1 0
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@ -455,11 +455,11 @@
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;; instructions to be processed in the "imuldiv" unit.
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(define_function_unit "adder" 1 1
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(and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000"))
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(and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3900,r6000,r4300,r5000"))
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3 0)
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(define_function_unit "adder" 1 1
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(and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r3900,r6000"))
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(and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3900,r6000"))
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2 0)
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(define_function_unit "adder" 1 1
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@ -467,11 +467,11 @@
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1 0)
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(define_function_unit "adder" 1 1
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(and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300"))
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(and (eq_attr "type" "fadd") (eq_attr "cpu" "r3900,r6000,r4300"))
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4 0)
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(define_function_unit "adder" 1 1
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(and (eq_attr "type" "fadd") (eq_attr "cpu" "r3000,r3900"))
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(and (eq_attr "type" "fadd") (eq_attr "cpu" "r3900"))
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2 0)
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(define_function_unit "adder" 1 1
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@ -480,22 +480,22 @@
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(define_function_unit "adder" 1 1
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(and (eq_attr "type" "fabs,fneg,fmove")
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(eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000"))
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(eq_attr "cpu" "r3900,r4600,r4650,r4300,r5000"))
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2 0)
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(define_function_unit "adder" 1 1
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(and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r3000,r3900,r4600,r4650,r5000"))
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(and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r3900,r4600,r4650,r5000"))
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1 0)
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(define_function_unit "mult" 1 1
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(and (eq_attr "type" "fmul")
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(and (eq_attr "mode" "SF")
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(eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
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(eq_attr "cpu" "r3900,r6000,r4600,r4650,r4300,r5000")))
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7 0)
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(define_function_unit "mult" 1 1
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(and (eq_attr "type" "fmul")
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(and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900,r5000")))
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(and (eq_attr "mode" "SF") (eq_attr "cpu" "r3900,r5000")))
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4 0)
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(define_function_unit "mult" 1 1
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@ -510,12 +510,12 @@
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(define_function_unit "mult" 1 1
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(and (eq_attr "type" "fmul")
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(and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000")))
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(and (eq_attr "mode" "DF") (eq_attr "cpu" "r3900,r6000,r4300,r5000")))
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8 0)
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(define_function_unit "mult" 1 1
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(and (eq_attr "type" "fmul")
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(and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900,r5000")))
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(and (eq_attr "mode" "DF") (eq_attr "cpu" "r3900,r5000")))
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5 0)
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(define_function_unit "mult" 1 1
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@ -526,12 +526,12 @@
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(define_function_unit "divide" 1 1
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(and (eq_attr "type" "fdiv")
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(and (eq_attr "mode" "SF")
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(eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
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(eq_attr "cpu" "r3900,r6000,r4600,r4650,r4300,r5000")))
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23 0)
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(define_function_unit "divide" 1 1
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(and (eq_attr "type" "fdiv")
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(and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900")))
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(and (eq_attr "mode" "SF") (eq_attr "cpu" "r3900")))
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12 0)
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(define_function_unit "divide" 1 1
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@ -552,12 +552,12 @@
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(define_function_unit "divide" 1 1
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(and (eq_attr "type" "fdiv")
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(and (eq_attr "mode" "DF")
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(eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300")))
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(eq_attr "cpu" "r3900,r6000,r4600,r4650,r4300")))
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36 0)
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(define_function_unit "divide" 1 1
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(and (eq_attr "type" "fdiv")
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(and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900")))
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(and (eq_attr "mode" "DF") (eq_attr "cpu" "r3900")))
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19 0)
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(define_function_unit "divide" 1 1
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@ -631,6 +631,7 @@
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;; Include scheduling descriptions.
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(include "3000.md")
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(include "4130.md")
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(include "5400.md")
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(include "5500.md")
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