pa.md (UNSPEC_MEMORY_BARRIER): New unspec enum.
gcc * config/pa/pa.md (UNSPEC_MEMORY_BARRIER): New unspec enum. Update comment for atomic instructions. (atomic_storeqi, atomic_storehi, atomic_storesi, atomic_storesf, atomic_loaddf, atomic_loaddf_1, atomic_storedf, atomic_storedf_1): Remove. (atomic_loaddi): Revise fence expansion to only emit fence prior to load for __ATOMIC_SEQ_CST model. (atomic_loaddi_1): Remove float register target. (atomic_storedi): Handle CONST_INT values. (atomic_storedi_1): Remove float register source. Add special case for zero value. (memory_barrier): New expander and insn. libgcc * config/pa/linux-atomic.c: Update comment. (FETCH_AND_OP_2, OP_AND_FETCH_2, FETCH_AND_OP_WORD, OP_AND_FETCH_WORD, COMPARE_AND_SWAP_2, __sync_val_compare_and_swap_4, SYNC_LOCK_TEST_AND_SET_2, __sync_lock_test_and_set_4): Use __ATOMIC_RELAXED for atomic loads. (SYNC_LOCK_RELEASE_1): New define. Use __sync_synchronize() and unordered store to release lock. (__sync_lock_release_8): Likewise. (SYNC_LOCK_RELEASE_2): Remove define. From-SVN: r263488
This commit is contained in:
John David Anglin
parent
8be591a9cd
commit
2b1969f635
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@ -1,3 +1,18 @@
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2018-08-11 John David Anglin <danglin@gcc.gnu.org>
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* config/pa/pa.md (UNSPEC_MEMORY_BARRIER): New unspec enum.
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Update comment for atomic instructions.
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(atomic_storeqi, atomic_storehi, atomic_storesi, atomic_storesf,
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atomic_loaddf, atomic_loaddf_1, atomic_storedf, atomic_storedf_1):
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Remove.
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(atomic_loaddi): Revise fence expansion to only emit fence prior to
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load for __ATOMIC_SEQ_CST model.
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(atomic_loaddi_1): Remove float register target.
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(atomic_storedi): Handle CONST_INT values.
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(atomic_storedi_1): Remove float register source. Add special case
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for zero value.
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(memory_barrier): New expander and insn.
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2018-08-11 Jakub Jelinek <jakub@redhat.com>
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PR tree-optimization/86835
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@ -84,6 +84,7 @@
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UNSPEC_TLSGD_PIC
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UNSPEC_TLSLDM_PIC
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UNSPEC_TLSIE_PIC
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UNSPEC_MEMORY_BARRIER
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])
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;; UNSPEC_VOLATILE:
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@ -9955,84 +9956,8 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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;; doubleword loads and stores are not guaranteed to be atomic
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;; when referencing the I/O address space.
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;; The kernel cmpxchg operation on linux is not atomic with respect to
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;; memory stores on SMP machines, so we must do stores using a cmpxchg
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;; operation.
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;; These patterns are at the bottom so the non atomic versions are preferred.
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;; Implement atomic QImode store using exchange.
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(define_expand "atomic_storeqi"
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[(match_operand:QI 0 "memory_operand") ;; memory
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(match_operand:QI 1 "register_operand") ;; val out
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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if (TARGET_SYNC_LIBCALL)
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{
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rtx mem = operands[0];
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rtx val = operands[1];
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if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
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DONE;
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}
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FAIL;
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})
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;; Implement atomic HImode stores using exchange.
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(define_expand "atomic_storehi"
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[(match_operand:HI 0 "memory_operand") ;; memory
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(match_operand:HI 1 "register_operand") ;; val out
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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if (TARGET_SYNC_LIBCALL)
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{
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rtx mem = operands[0];
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rtx val = operands[1];
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if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
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DONE;
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}
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FAIL;
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})
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;; Implement atomic SImode store using exchange.
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(define_expand "atomic_storesi"
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[(match_operand:SI 0 "memory_operand") ;; memory
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(match_operand:SI 1 "register_operand") ;; val out
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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if (TARGET_SYNC_LIBCALL)
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{
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rtx mem = operands[0];
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rtx val = operands[1];
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if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
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DONE;
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}
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FAIL;
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})
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;; Implement atomic SFmode store using exchange.
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(define_expand "atomic_storesf"
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[(match_operand:SF 0 "memory_operand") ;; memory
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(match_operand:SF 1 "register_operand") ;; val out
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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if (TARGET_SYNC_LIBCALL)
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{
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rtx mem = operands[0];
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rtx val = operands[1];
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if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
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DONE;
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}
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FAIL;
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})
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;; Implement atomic DImode load using 64-bit floating point load.
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(define_expand "atomic_loaddi"
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@ -10048,47 +9973,39 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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model = memmodel_from_int (INTVAL (operands[2]));
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operands[1] = force_reg (SImode, XEXP (operands[1], 0));
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expand_mem_thread_fence (model);
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emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
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if (is_mm_seq_cst (model))
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expand_mem_thread_fence (model);
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emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
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expand_mem_thread_fence (model);
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DONE;
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})
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(define_insn "atomic_loaddi_1"
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[(set (match_operand:DI 0 "register_operand" "=f,r")
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(mem:DI (match_operand:SI 1 "register_operand" "r,r")))
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(clobber (match_scratch:DI 2 "=X,f"))]
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[(set (match_operand:DI 0 "register_operand" "=r")
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(mem:DI (match_operand:SI 1 "register_operand" "r")))
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(clobber (match_scratch:DI 2 "=f"))]
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"!TARGET_64BIT && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT"
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"@
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{fldds|fldd} 0(%1),%0
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{fldds|fldd} 0(%1),%2\n\t{fstds|fstd} %2,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0\n\t{ldws|ldw} -12(%%sp),%R0"
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[(set_attr "type" "move,move")
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(set_attr "length" "4,16")])
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"{fldds|fldd} 0(%1),%2\n\t{fstds|fstd} %2,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0\n\t{ldws|ldw} -12(%%sp),%R0"
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[(set_attr "type" "move")
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(set_attr "length" "16")])
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;; Implement atomic DImode store.
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(define_expand "atomic_storedi"
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[(match_operand:DI 0 "memory_operand") ;; memory
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(match_operand:DI 1 "register_operand") ;; val out
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(match_operand:DI 1 "reg_or_cint_move_operand") ;; val out
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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enum memmodel model;
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if (TARGET_SYNC_LIBCALL)
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{
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rtx mem = operands[0];
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rtx val = operands[1];
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if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
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DONE;
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}
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if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
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FAIL;
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model = memmodel_from_int (INTVAL (operands[2]));
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operands[0] = force_reg (SImode, XEXP (operands[0], 0));
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if (operands[1] != CONST0_RTX (DImode))
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operands[1] = force_reg (DImode, operands[1]);
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expand_mem_thread_fence (model);
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emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
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if (is_mm_seq_cst (model))
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@ -10098,87 +10015,33 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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(define_insn "atomic_storedi_1"
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[(set (mem:DI (match_operand:SI 0 "register_operand" "r,r"))
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(match_operand:DI 1 "register_operand" "f,r"))
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(match_operand:DI 1 "reg_or_0_operand" "M,r"))
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(clobber (match_scratch:DI 2 "=X,f"))]
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"!TARGET_64BIT && !TARGET_DISABLE_FPREGS
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&& !TARGET_SOFT_FLOAT && !TARGET_SYNC_LIBCALL"
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"@
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{fstds|fstd} %1,0(%0)
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{stws|stw} %1,-16(%%sp)\n\t{stws|stw} %R1,-12(%%sp)\n\t{fldds|fldd} -16(%%sp),%2\n\t{fstds|fstd} %2,0(%0)"
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[(set_attr "type" "move,move")
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(set_attr "length" "4,16")])
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;; Implement atomic DFmode load using 64-bit floating point load.
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(define_expand "atomic_loaddf"
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[(match_operand:DF 0 "register_operand") ;; val out
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(match_operand:DF 1 "memory_operand") ;; memory
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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enum memmodel model;
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if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
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FAIL;
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model = memmodel_from_int (INTVAL (operands[2]));
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operands[1] = force_reg (SImode, XEXP (operands[1], 0));
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expand_mem_thread_fence (model);
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emit_insn (gen_atomic_loaddf_1 (operands[0], operands[1]));
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if (is_mm_seq_cst (model))
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expand_mem_thread_fence (model);
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DONE;
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})
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(define_insn "atomic_loaddf_1"
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[(set (match_operand:DF 0 "register_operand" "=f,r")
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(mem:DF (match_operand:SI 1 "register_operand" "r,r")))
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(clobber (match_scratch:DF 2 "=X,f"))]
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"!TARGET_64BIT && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT"
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"@
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{fldds|fldd} 0(%1),%0
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{fldds|fldd} 0(%1),%2\n\t{fstds|fstd} %2,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0\n\t{ldws|ldw} -12(%%sp),%R0"
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[(set_attr "type" "move,move")
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(set_attr "length" "4,16")])
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;; Implement atomic DFmode store using 64-bit floating point store.
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(define_expand "atomic_storedf"
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[(match_operand:DF 0 "memory_operand") ;; memory
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(match_operand:DF 1 "register_operand") ;; val out
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(match_operand:SI 2 "const_int_operand")] ;; model
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""
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{
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enum memmodel model;
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if (TARGET_SYNC_LIBCALL)
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{
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rtx mem = operands[0];
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rtx val = operands[1];
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if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
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DONE;
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}
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if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
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FAIL;
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model = memmodel_from_int (INTVAL (operands[2]));
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operands[0] = force_reg (SImode, XEXP (operands[0], 0));
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expand_mem_thread_fence (model);
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emit_insn (gen_atomic_storedf_1 (operands[0], operands[1]));
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if (is_mm_seq_cst (model))
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expand_mem_thread_fence (model);
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DONE;
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})
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(define_insn "atomic_storedf_1"
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[(set (mem:DF (match_operand:SI 0 "register_operand" "r,r"))
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(match_operand:DF 1 "register_operand" "f,r"))
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(clobber (match_scratch:DF 2 "=X,f"))]
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"!TARGET_64BIT && !TARGET_DISABLE_FPREGS
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&& !TARGET_SOFT_FLOAT && !TARGET_SYNC_LIBCALL"
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"@
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{fstds|fstd} %1,0(%0)
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{fstds|fstd} %%fr0,0(%0)
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{stws|stw} %1,-16(%%sp)\n\t{stws|stw} %R1,-12(%%sp)\n\t{fldds|fldd} -16(%%sp),%2\n\t{fstds|fstd} %2,0(%0)"
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[(set_attr "type" "move,move")
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(set_attr "length" "4,16")])
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;; PA 2.0 hardware supports out-of-order execution of loads and stores, so
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;; we need a memory barrier to enforce program order for memory references.
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;; Since we want PA 1.x code to be PA 2.0 compatible, we also need the
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;; barrier when generating PA 1.x code.
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(define_expand "memory_barrier"
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[(set (match_dup 0)
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(unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))]
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""
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{
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operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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MEM_VOLATILE_P (operands[0]) = 1;
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})
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(define_insn "*memory_barrier"
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[(set (match_operand:BLK 0 "" "")
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(unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))]
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""
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"sync"
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[(set_attr "type" "binary")
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(set_attr "length" "4")])
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@ -1,3 +1,15 @@
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2018-08-11 John David Anglin <danglin@gcc.gnu.org>
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* config/pa/linux-atomic.c: Update comment.
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(FETCH_AND_OP_2, OP_AND_FETCH_2, FETCH_AND_OP_WORD, OP_AND_FETCH_WORD,
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COMPARE_AND_SWAP_2, __sync_val_compare_and_swap_4,
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SYNC_LOCK_TEST_AND_SET_2, __sync_lock_test_and_set_4): Use
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__ATOMIC_RELAXED for atomic loads.
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(SYNC_LOCK_RELEASE_1): New define. Use __sync_synchronize() and
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unordered store to release lock.
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(__sync_lock_release_8): Likewise.
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(SYNC_LOCK_RELEASE_2): Remove define.
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2018-08-02 Nicolas Pitre <nico@fluxnic.net>
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PR libgcc/86512
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|
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@ -28,14 +28,9 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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#define EBUSY 16
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#define ENOSYS 251
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/* All PA-RISC implementations supported by linux have strongly
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ordered loads and stores. Only cache flushes and purges can be
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delayed. The data cache implementations are all globally
|
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coherent. Thus, there is no need to synchonize memory accesses.
|
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GCC automatically issues a asm memory barrier when it encounters
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a __sync_synchronize builtin. Thus, we do not need to define this
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builtin.
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/* PA-RISC 2.0 supports out-of-order execution for loads and stores.
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Thus, we need to synchonize memory accesses. For more info, see:
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"Advanced Performance Features of the 64-bit PA-8000" by Doug Hunt.
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We implement byte, short and int versions of each atomic operation
|
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using the kernel helper defined below. There is no support for
|
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|
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@ -119,7 +114,7 @@ __kernel_cmpxchg2 (void *mem, const void *oldval, const void *newval,
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long failure; \
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\
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do { \
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tmp = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
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tmp = __atomic_load_n (ptr, __ATOMIC_RELAXED); \
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newval = PFX_OP (tmp INF_OP val); \
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failure = __kernel_cmpxchg2 (ptr, &tmp, &newval, INDEX); \
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||||
} while (failure != 0); \
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|
@ -156,7 +151,7 @@ FETCH_AND_OP_2 (nand, ~, &, signed char, 1, 0)
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long failure; \
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\
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||||
do { \
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tmp = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
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tmp = __atomic_load_n (ptr, __ATOMIC_RELAXED); \
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newval = PFX_OP (tmp INF_OP val); \
|
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failure = __kernel_cmpxchg2 (ptr, &tmp, &newval, INDEX); \
|
||||
} while (failure != 0); \
|
||||
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|
@ -193,7 +188,7 @@ OP_AND_FETCH_2 (nand, ~, &, signed char, 1, 0)
|
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long failure; \
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\
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||||
do { \
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tmp = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
|
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tmp = __atomic_load_n (ptr, __ATOMIC_RELAXED); \
|
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failure = __kernel_cmpxchg (ptr, tmp, PFX_OP (tmp INF_OP val)); \
|
||||
} while (failure != 0); \
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\
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||||
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|
@ -215,7 +210,7 @@ FETCH_AND_OP_WORD (nand, ~, &)
|
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long failure; \
|
||||
\
|
||||
do { \
|
||||
tmp = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
|
||||
tmp = __atomic_load_n (ptr, __ATOMIC_RELAXED); \
|
||||
failure = __kernel_cmpxchg (ptr, tmp, PFX_OP (tmp INF_OP val)); \
|
||||
} while (failure != 0); \
|
||||
\
|
||||
|
|
@ -241,7 +236,7 @@ typedef unsigned char bool;
|
|||
\
|
||||
while (1) \
|
||||
{ \
|
||||
actual_oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
|
||||
actual_oldval = __atomic_load_n (ptr, __ATOMIC_RELAXED); \
|
||||
\
|
||||
if (__builtin_expect (oldval != actual_oldval, 0)) \
|
||||
return actual_oldval; \
|
||||
|
|
@ -273,7 +268,7 @@ __sync_val_compare_and_swap_4 (int *ptr, int oldval, int newval)
|
|||
|
||||
while (1)
|
||||
{
|
||||
actual_oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST);
|
||||
actual_oldval = __atomic_load_n (ptr, __ATOMIC_RELAXED);
|
||||
|
||||
if (__builtin_expect (oldval != actual_oldval, 0))
|
||||
return actual_oldval;
|
||||
|
|
@ -300,7 +295,7 @@ TYPE HIDDEN \
|
|||
long failure; \
|
||||
\
|
||||
do { \
|
||||
oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
|
||||
oldval = __atomic_load_n (ptr, __ATOMIC_RELAXED); \
|
||||
failure = __kernel_cmpxchg2 (ptr, &oldval, &val, INDEX); \
|
||||
} while (failure != 0); \
|
||||
\
|
||||
|
|
@ -318,38 +313,31 @@ __sync_lock_test_and_set_4 (int *ptr, int val)
|
|||
int oldval;
|
||||
|
||||
do {
|
||||
oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST);
|
||||
oldval = __atomic_load_n (ptr, __ATOMIC_RELAXED);
|
||||
failure = __kernel_cmpxchg (ptr, oldval, val);
|
||||
} while (failure != 0);
|
||||
|
||||
return oldval;
|
||||
}
|
||||
|
||||
#define SYNC_LOCK_RELEASE_2(TYPE, WIDTH, INDEX) \
|
||||
void HIDDEN
|
||||
__sync_lock_release_8 (long long *ptr)
|
||||
{
|
||||
/* All accesses must be complete before we release the lock. */
|
||||
__sync_synchronize ();
|
||||
*(double *)ptr = 0;
|
||||
}
|
||||
|
||||
#define SYNC_LOCK_RELEASE_1(TYPE, WIDTH) \
|
||||
void HIDDEN \
|
||||
__sync_lock_release_##WIDTH (TYPE *ptr) \
|
||||
{ \
|
||||
TYPE oldval, zero = 0; \
|
||||
long failure; \
|
||||
\
|
||||
do { \
|
||||
oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
|
||||
failure = __kernel_cmpxchg2 (ptr, &oldval, &zero, INDEX); \
|
||||
} while (failure != 0); \
|
||||
/* All accesses must be complete before we release \
|
||||
the lock. */ \
|
||||
__sync_synchronize (); \
|
||||
*ptr = 0; \
|
||||
}
|
||||
|
||||
SYNC_LOCK_RELEASE_2 (long long, 8, 3)
|
||||
SYNC_LOCK_RELEASE_2 (short, 2, 1)
|
||||
SYNC_LOCK_RELEASE_2 (signed char, 1, 0)
|
||||
|
||||
void HIDDEN
|
||||
__sync_lock_release_4 (int *ptr)
|
||||
{
|
||||
long failure;
|
||||
int oldval;
|
||||
|
||||
do {
|
||||
oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST);
|
||||
failure = __kernel_cmpxchg (ptr, oldval, 0);
|
||||
} while (failure != 0);
|
||||
}
|
||||
SYNC_LOCK_RELEASE_1 (int, 4)
|
||||
SYNC_LOCK_RELEASE_1 (short, 2)
|
||||
SYNC_LOCK_RELEASE_1 (signed char, 1)
|
||||
|
|
|
|||
Loading…
Reference in New Issue