[arm] Implement DImode SIMD32 intrinsics
This patch implements some more SIMD32, but these ones have a DImode result+addend. Apart from that there's nothing too exciting about them. Bootstrapped and tested on arm-none-linux-gnueabihf. * config/arm/arm.md (arm_<simd32_op>): New define_insn. * config/arm/arm_acle.h (__smlald, __smlaldx, __smlsld, __smlsldx): Define. * config/arm/arm_acle.h: Define builtins for the above. * config/arm/iterators.md (SIMD32_DIMODE): New int_iterator. (simd32_op): Handle the above. * config/arm/unspecs.md: Define unspecs for the above. * gcc.target/arm/acle/simd32.c: Update test. From-SVN: r276147
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@ -1,3 +1,13 @@
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2019-09-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/arm/arm.md (arm_<simd32_op>): New define_insn.
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* config/arm/arm_acle.h (__smlald, __smlaldx, __smlsld, __smlsldx):
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Define.
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* config/arm/arm_acle.h: Define builtins for the above.
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* config/arm/iterators.md (SIMD32_DIMODE): New int_iterator.
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(simd32_op): Handle the above.
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* config/arm/unspecs.md: Define unspecs for the above.
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2019-09-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/arm/arm.md (arm_<simd32_op>): New define_insn.
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@ -5088,6 +5088,17 @@
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[(set_attr "predicable" "yes")
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(set_attr "type" "alu_dsp_reg")])
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(define_insn "arm_<simd32_op>"
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[(set (match_operand:DI 0 "s_register_operand" "=r")
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(unspec:DI
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[(match_operand:SI 1 "s_register_operand" "r")
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(match_operand:SI 2 "s_register_operand" "r")
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(match_operand:DI 3 "s_register_operand" "0")] SIMD32_DIMODE))]
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"TARGET_INT_SIMD"
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"<simd32_op>%?\\t%Q0, %R0, %1, %2"
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[(set_attr "predicable" "yes")
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(set_attr "type" "smlald")])
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(define_expand "extendsfdf2"
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[(set (match_operand:DF 0 "s_register_operand")
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(float_extend:DF (match_operand:SF 1 "s_register_operand")))]
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@ -403,8 +403,37 @@ __usada8 (uint8x4_t __a, uint8x4_t __b, uint32_t __c)
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return __builtin_arm_usada8 (__a, __b, __c);
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}
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__extension__ extern __inline int64_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__smlald (int16x2_t __a, int16x2_t __b, int64_t __c)
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{
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return __builtin_arm_smlald (__a, __b, __c);
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}
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__extension__ extern __inline int64_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__smlaldx (int16x2_t __a, int16x2_t __b, int64_t __c)
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{
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return __builtin_arm_smlaldx (__a, __b, __c);
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}
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__extension__ extern __inline int64_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__smlsld (int16x2_t __a, int16x2_t __b, int64_t __c)
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{
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return __builtin_arm_smlsld (__a, __b, __c);
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}
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__extension__ extern __inline int64_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__smlsldx (int16x2_t __a, int16x2_t __b, int64_t __c)
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{
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return __builtin_arm_smlsldx (__a, __b, __c);
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}
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#endif
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#pragma GCC push_options
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#ifdef __ARM_FEATURE_CRC32
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#ifdef __ARM_FP
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@ -75,3 +75,7 @@ VAR1 (BINOP, smusd, si)
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VAR1 (BINOP, smusdx, si)
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VAR1 (UBINOP, usad8, si)
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VAR1 (UBINOP, usada8, si)
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VAR1 (TERNOP, smlald, di)
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VAR1 (TERNOP, smlaldx, di)
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VAR1 (TERNOP, smlsld, di)
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VAR1 (TERNOP, smlsldx, di)
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@ -443,6 +443,9 @@
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UNSPEC_UQSUB16 UNSPEC_SMUSD UNSPEC_SMUSDX
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UNSPEC_SXTAB16 UNSPEC_UXTAB16 UNSPEC_USAD8])
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(define_int_iterator SIMD32_DIMODE [UNSPEC_SMLALD UNSPEC_SMLALDX
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UNSPEC_SMLSLD UNSPEC_SMLSLDX])
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(define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH])
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(define_int_iterator VFM_LANE_AS [UNSPEC_VFMA_LANE UNSPEC_VFMS_LANE])
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(UNSPEC_UQSAX "uqsax") (UNSPEC_UQSUB16 "uqsub16")
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(UNSPEC_SMUSD "smusd") (UNSPEC_SMUSDX "smusdx")
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(UNSPEC_SXTAB16 "sxtab16") (UNSPEC_UXTAB16 "uxtab16")
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(UNSPEC_USAD8 "usad8")])
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(UNSPEC_USAD8 "usad8") (UNSPEC_SMLALD "smlald")
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(UNSPEC_SMLALDX "smlaldx") (UNSPEC_SMLSLD "smlsld")
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(UNSPEC_SMLSLDX "smlsldx")])
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;; Both kinds of return insn.
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(define_code_iterator RETURNS [return simple_return])
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@ -123,6 +123,10 @@
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UNSPEC_SMUSDX ; Represent the SMUSDX operation.
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UNSPEC_USAD8 ; Represent the USAD8 operation.
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UNSPEC_USADA8 ; Represent the USADA8 operation.
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UNSPEC_SMLALD ; Represent the SMLALD operation.
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UNSPEC_SMLALDX ; Represent the SMLALDX operation.
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UNSPEC_SMLSLD ; Represent the SMLSLD operation.
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UNSPEC_SMLSLDX ; Represent the SMLSLDX operation.
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])
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@ -1,3 +1,7 @@
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2019-09-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* gcc.target/arm/acle/simd32.c: Update test.
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2019-09-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* lib/target-supports.exp
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@ -244,3 +244,35 @@ test_usada8 (uint8x4_t a, uint8x4_t b, uint32_t c)
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}
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/* { dg-final { scan-assembler-times "\tusada8\t...?, ...?, ...?, ...?" 1 } } */
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int64_t
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test_smlald (int16x2_t a, int16x2_t b, int64_t c)
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{
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return __smlald (a, b, c);
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}
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/* { dg-final { scan-assembler-times "\tsmlald\t...?, ...?, ...?, ...?" 1 } } */
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int64_t
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test_smlaldx (int16x2_t a, int16x2_t b, int64_t c)
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{
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return __smlaldx (a, b, c);
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}
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/* { dg-final { scan-assembler-times "\tsmlaldx\t...?, ...?, ...?, ...?" 1 } } */
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int64_t
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test_smlsld (int16x2_t a, int16x2_t b, int64_t c)
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{
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return __smlsld (a, b, c);
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}
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/* { dg-final { scan-assembler-times "\tsmlsld\t...?, ...?, ...?, ...?" 1 } } */
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int64_t
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test_smlsldx (int16x2_t a, int16x2_t b, int64_t c)
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{
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return __smlsldx (a, b, c);
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}
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/* { dg-final { scan-assembler-times "\tsmlsldx\t...?, ...?, ...?, ...?" 1 } } */
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