Richard Stallman
parent
00fe048c3c
commit
2bb7a0f55b
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@ -206,6 +206,9 @@
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"TARGET_80387"
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"")
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;; The `ble' and `blt' patterns can reverse a compare, so we must allow
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;; an immediate operand as operand 0 in the recognizers below.
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(define_insn ""
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[(set (cc0)
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(compare (match_operand:DF 0 "general_operand" "f")
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@ -356,9 +359,24 @@
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;; General case of fullword move.
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;; If generating PIC code and operands[1] is a symbolic CONST, emit a
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;; move to get the address of the symbolic object from the GOT.
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(define_expand "movsi"
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[(set (match_operand:SI 0 "general_operand" "")
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(match_operand:SI 1 "general_operand" ""))]
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""
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"
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{
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extern int flag_pic;
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if (flag_pic && SYMBOLIC_CONST (operands[1]))
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emit_pic_move (operands, SImode);
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}")
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;; On i486, incl reg is faster than movl $1,reg.
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(define_insn "movsi"
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(define_insn ""
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[(set (match_operand:SI 0 "general_operand" "=g,r")
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(match_operand:SI 1 "general_operand" "ri,m"))]
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""
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@ -1490,10 +1508,10 @@
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;; Remainder instructions.
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(define_insn "divmodsi4"
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[(set (match_operand:SI 0 "general_operand" "=a")
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(div:SI (match_operand:SI 1 "general_operand" "0")
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[(set (match_operand:SI 0 "register_operand" "=a")
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(div:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "general_operand" "rm")))
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(set (match_operand:SI 3 "general_operand" "=&d")
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(set (match_operand:SI 3 "register_operand" "=&d")
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(mod:SI (match_dup 1) (match_dup 2)))]
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""
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"*
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@ -1507,20 +1525,20 @@
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}")
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(define_insn "divmodhi4"
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[(set (match_operand:HI 0 "general_operand" "=a")
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(div:HI (match_operand:HI 1 "general_operand" "0")
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[(set (match_operand:HI 0 "register_operand" "=a")
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(div:HI (match_operand:HI 1 "register_operand" "0")
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(match_operand:HI 2 "general_operand" "rm")))
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(set (match_operand:HI 3 "general_operand" "=&d")
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(set (match_operand:HI 3 "register_operand" "=&d")
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(mod:HI (match_dup 1) (match_dup 2)))]
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""
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"cwtd\;idiv%W0 %2")
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;; ??? Can we make gcc zero extend operand[0]?
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(define_insn "udivmodsi4"
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[(set (match_operand:SI 0 "general_operand" "=a")
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(udiv:SI (match_operand:SI 1 "general_operand" "0")
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[(set (match_operand:SI 0 "register_operand" "=a")
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(udiv:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "general_operand" "rm")))
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(set (match_operand:SI 3 "general_operand" "=&d")
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(set (match_operand:SI 3 "register_operand" "=&d")
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(umod:SI (match_dup 1) (match_dup 2)))]
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""
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"*
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@ -1531,10 +1549,10 @@
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;; ??? Can we make gcc zero extend operand[0]?
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(define_insn "udivmodhi4"
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[(set (match_operand:HI 0 "general_operand" "=a")
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(udiv:HI (match_operand:HI 1 "general_operand" "0")
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[(set (match_operand:HI 0 "register_operand" "=a")
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(udiv:HI (match_operand:HI 1 "register_operand" "0")
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(match_operand:HI 2 "general_operand" "rm")))
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(set (match_operand:HI 3 "general_operand" "=&d")
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(set (match_operand:HI 3 "register_operand" "=&d")
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(umod:HI (match_dup 1) (match_dup 2)))]
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""
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"*
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@ -1547,10 +1565,10 @@
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;;this should be a valid double division which we may want to add
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(define_insn ""
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[(set (match_operand:SI 0 "general_operand" "=a")
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(udiv:DI (match_operand:DI 1 "general_operand" "a")
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(match_operand:SI 2 "general_operand" "rm")))
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(set (match_operand:SI 3 "general_operand" "=d")
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[(set (match_operand:SI 0 "register_operand" "=a")
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(udiv:DI (match_operand:DI 1 "register_operand" "a")
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(match_operand:SI 2 "general_operand" "rm")))
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(set (match_operand:SI 3 "register_operand" "=d")
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(umod:SI (match_dup 1) (match_dup 2)))]
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""
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"div%L0 %2,%0")
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@ -2605,7 +2623,7 @@
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;; bt on the MEM directly.
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(define_insn ""
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[(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "q")
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[(set (cc0) (zero_extract (match_operand:QI 0 "register_operand" "q")
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(const_int 1)
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(match_operand:SI 1 "general_operand" "ri")))]
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""
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@ -2625,6 +2643,34 @@
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RET;
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}")
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(define_insn ""
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[(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
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(const_int 1)
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(match_operand:SI 1 "general_operand" "ri")))
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(clobber (match_scratch:SI 2 "=&r"))]
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""
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"*
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{
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/* Copy memory to scratch register; pretend it was there to start with. */
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if (GET_CODE (operands[0]) == MEM)
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{
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output_asm_insn (AS2 (mov%L2,%0,%2), operands);
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operands[0] = operands[2];
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}
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if (GET_CODE (operands[1]) == CONST_INT)
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{
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operands[1] = gen_rtx (CONST_INT, VOIDmode, 1 << INTVAL (operands[1]));
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output_asm_insn (AS2 (test%L0,%1,%0), operands);
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}
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else
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{
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operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]));
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cc_status.flags |= CC_Z_IN_NOT_C;
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output_asm_insn (AS2 (bt%L0,%1,%0), operands);
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}
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RET;
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}")
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(define_insn ""
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[(set (cc0) (zero_extract (match_operand:HI 0 "nonimmediate_operand" "r")
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(const_int 1)
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@ -2673,7 +2719,7 @@
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""
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"*
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{
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if (cc_status.flags & CC_Z_IN_NOT_C)
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if (cc_prev_status.flags & CC_Z_IN_NOT_C)
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return AS1 (setnb,%0);
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else
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return AS1 (sete,%0);
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@ -2686,7 +2732,7 @@
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""
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"*
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{
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if (cc_status.flags & CC_Z_IN_NOT_C)
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if (cc_prev_status.flags & CC_Z_IN_NOT_C)
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return AS1 (setb,%0);
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else
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return AS1 (setne,%0);
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@ -2753,7 +2799,7 @@
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""
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"*
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{
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if (cc_status.flags & CC_Z_IN_NOT_C)
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if (cc_prev_status.flags & CC_Z_IN_NOT_C)
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return \"jnc %l0\";
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else
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return \"je %l0\";
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@ -2768,7 +2814,7 @@
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""
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"*
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{
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if (cc_status.flags & CC_Z_IN_NOT_C)
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if (cc_prev_status.flags & CC_Z_IN_NOT_C)
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return \"jc %l0\";
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else
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return \"jne %l0\";
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@ -2915,7 +2961,7 @@
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""
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"*
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{
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if (cc_status.flags & CC_Z_IN_NOT_C)
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if (cc_prev_status.flags & CC_Z_IN_NOT_C)
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return \"jc %l0\";
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else
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return \"jne %l0\";
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@ -2930,7 +2976,7 @@
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""
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"*
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{
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if (cc_status.flags & CC_Z_IN_NOT_C)
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if (cc_prev_status.flags & CC_Z_IN_NOT_C)
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return \"jnc %l0\";
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else
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return \"je %l0\";
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@ -3018,7 +3064,7 @@
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"jmp %l0")
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(define_insn "indirect_jump"
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[(set (pc) (match_operand:SI 0 "register_operand" "a"))]
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[(set (pc) (match_operand:SI 0 "general_operand" "rm"))]
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""
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"*
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{
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@ -3027,6 +3073,98 @@
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return AS1 (jmp,%*%0);
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}")
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;; Implement switch statements when generating PIC code. Switches are
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;; implemented by `tablejump' when not using -fpic.
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;; Emit code here to do the range checking and make the index zero based.
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(define_expand "casesi"
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[(parallel
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[(set (pc)
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(if_then_else (leu (minus:SI
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(match_operand:SI 0 "general_operand" "")
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(match_operand:SI 1 "const_int_operand" ""))
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(match_operand:SI 2 "const_int_operand" ""))
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(plus:SI (mem:SI (plus:SI (pc)
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(minus:SI (match_dup 0)
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(match_dup 1))))
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(label_ref (match_operand 3 "" "")))
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(pc)))
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(use (label_ref (match_operand 4 "" "")))
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(clobber (match_scratch:SI 5 ""))])]
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"flag_pic"
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"
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{
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rtx reg = gen_reg_rtx (SImode);
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current_function_uses_pic_offset_table = 1;
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emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
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emit_insn (gen_cmpsi (reg, operands[2]));
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emit_jump_insn (gen_bgtu (operands[4]));
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operands[0] = reg;
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operands[1] = CONST0_RTX (SImode);
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}")
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;; Implement a casesi insn.
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;; Each entry in the "addr_diff_vec" looks like this as the result of the
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;; two rules below:
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;;
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;; .long _GLOBAL_OFFSET_TABLE_+[.-.L2]
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;;
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;; 1. An expression involving an external reference may only use the
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;; addition operator, and only with an assembly-time constant.
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;; The example above satisfies this because ".-.L2" is a constant.
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;;
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;; 2. The symbol _GLOBAL_OFFSET_TABLE_ is magic, and at link time is
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;; given the value of "GOT - .", where GOT is the actual address of
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;; the Global Offset Table. Therefore, the .long above actually
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;; stores the value "( GOT - . ) + [ . - .L2 ]", or "GOT - .L2". The
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;; expression "GOT - .L2" by itself would generate an error from as(1).
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;;
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;; The pattern below emits code that looks like this:
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;;
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;; movl %ebx,reg
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;; subl TABLE@GOTOFF(%ebx,index,4),reg
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;; jmp reg
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;;
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;; The addr_diff_vec contents may be directly referenced with @GOTOFF, since
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;; the addr_diff_vec is known to be part of this module.
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;;
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;; The subl above calculates "GOT - (( GOT - . ) + [ . - .L2 ])", which
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;; evaluates to just ".L2".
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(define_insn ""
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[(set (pc)
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(if_then_else (leu (minus:SI
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(match_operand:SI 0 "general_operand" "r")
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(match_operand:SI 1 "const_int_operand" "i"))
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(match_operand:SI 2 "const_int_operand" "i"))
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(plus:SI (mem:SI (plus:SI (pc)
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(minus:SI (match_dup 0)
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(match_dup 1))))
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(label_ref (match_operand 3 "" "")))
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(pc)))
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(use (label_ref (match_operand 4 "" "")))
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(clobber (match_scratch:SI 5 "=&r"))]
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""
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"*
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{
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rtx xops[4];
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xops[0] = pic_offset_table_rtx;
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xops[1] = operands[5];
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xops[2] = operands[3];
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xops[3] = operands[0];
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output_asm_insn (AS2 (mov%L1,%0,%1), xops);
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output_asm_insn (\"sub%L1 %l2@GOTOFF(%0,%3,4),%1\", xops);
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output_asm_insn (AS1 (jmp,%*%1), xops);
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ASM_OUTPUT_ALIGN_CODE (asm_out_file);
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RET;
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}")
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(define_insn "tablejump"
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[(set (pc) (match_operand:SI 0 "general_operand" "rm"))
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(use (label_ref (match_operand 1 "" "")))]
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@ -3038,9 +3176,31 @@
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return AS1 (jmp,%*%0);
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}")
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;; Call insns.
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;; If generating PIC code, the predicate indirect_operand will fail
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;; for operands[0] containing symbolic references on all of the named
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;; call* patterns. Each named pattern is followed by an unnamed pattern
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;; that matches any call to a symbolic CONST (ie, a symbol_ref). The
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;; unnamed patterns are only used while generating PIC code, because
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;; otherwise the named patterns match.
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;; Call subroutine returning no value.
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(define_insn "call_pop"
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(define_expand "call_pop"
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[(parallel [(call (match_operand:QI 0 "indirect_operand" "")
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(match_operand:SI 1 "general_operand" ""))
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(set (reg:SI 7)
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(plus:SI (reg:SI 7)
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(match_operand:SI 3 "immediate_operand" "")))])]
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""
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"
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{
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if (flag_pic)
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current_function_uses_pic_offset_table = 1;
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}")
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(define_insn ""
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[(call (match_operand:QI 0 "indirect_operand" "m")
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(match_operand:SI 1 "general_operand" "g"))
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(set (reg:SI 7) (plus:SI (reg:SI 7)
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@ -3058,7 +3218,26 @@
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return AS1 (call,%P0);
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}")
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(define_insn "call"
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(define_insn ""
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[(call (mem:QI (match_operand:SI 0 "symbolic_operand" ""))
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(match_operand:SI 1 "general_operand" "g"))
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(set (reg:SI 7) (plus:SI (reg:SI 7)
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(match_operand:SI 3 "immediate_operand" "i")))]
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""
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"call %P0")
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(define_expand "call"
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[(call (match_operand:QI 0 "indirect_operand" "")
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(match_operand:SI 1 "general_operand" ""))]
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;; Operand 1 not used on the i386.
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""
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"
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{
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if (flag_pic)
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current_function_uses_pic_offset_table = 1;
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}")
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(define_insn ""
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[(call (match_operand:QI 0 "indirect_operand" "m")
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(match_operand:SI 1 "general_operand" "g"))]
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;; Operand 1 not used on the i386.
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@ -3075,10 +3254,31 @@
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return AS1 (call,%P0);
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}")
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(define_insn ""
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[(call (mem:QI (match_operand:SI 0 "symbolic_operand" ""))
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(match_operand:SI 1 "general_operand" "g"))]
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;; Operand 1 not used on the i386.
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""
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"call %P0")
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;; Call subroutine, returning value in operand 0
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;; (which must be a hard register).
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(define_insn "call_value_pop"
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(define_expand "call_value_pop"
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[(parallel [(set (match_operand 0 "" "")
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(call (match_operand:QI 1 "indirect_operand" "")
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(match_operand:SI 2 "general_operand" "")))
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(set (reg:SI 7)
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(plus:SI (reg:SI 7)
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(match_operand:SI 4 "immediate_operand" "")))])]
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""
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"
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{
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if (flag_pic)
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current_function_uses_pic_offset_table = 1;
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}")
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(define_insn ""
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[(set (match_operand 0 "" "=rf")
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(call (match_operand:QI 1 "indirect_operand" "m")
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(match_operand:SI 2 "general_operand" "g")))
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@ -3099,7 +3299,28 @@
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RET;
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}")
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(define_insn "call_value"
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(define_insn ""
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[(set (match_operand 0 "" "=rf")
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(call (mem:QI (match_operand:SI 1 "symbolic_operand" ""))
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(match_operand:SI 2 "general_operand" "g")))
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(set (reg:SI 7) (plus:SI (reg:SI 7)
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(match_operand:SI 4 "immediate_operand" "i")))]
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""
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"call %P1")
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(define_expand "call_value"
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[(set (match_operand 0 "" "")
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(call (match_operand:QI 1 "indirect_operand" "")
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(match_operand:SI 2 "general_operand" "")))]
|
||||
;; Operand 2 not used on the i386.
|
||||
""
|
||||
"
|
||||
{
|
||||
if (flag_pic)
|
||||
current_function_uses_pic_offset_table = 1;
|
||||
}")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand 0 "" "=rf")
|
||||
(call (match_operand:QI 1 "indirect_operand" "m")
|
||||
(match_operand:SI 2 "general_operand" "g")))]
|
||||
|
|
@ -3119,6 +3340,14 @@
|
|||
RET;
|
||||
}")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand 0 "" "=rf")
|
||||
(call (mem:QI (match_operand:SI 1 "symbolic_operand" ""))
|
||||
(match_operand:SI 2 "general_operand" "g")))]
|
||||
;; Operand 2 not used on the i386.
|
||||
""
|
||||
"call %P1")
|
||||
|
||||
;; Insn emitted into the body of a function to return from a function.
|
||||
;; This is only done if the function's epilogue is known to be simple.
|
||||
;; See comments for simple_386_epilogue in i386.c.
|
||||
|
|
|
|||
Loading…
Reference in New Issue