configure.in: Test for PowerPC mfcr field support in assembler.
2003-07-07 David Edelsohn <edelsohn@gnu.org>
Fariborz Jahanian <fjahanian@apple.com>
* configure.in: Test for PowerPC mfcr field support in assembler.
* config.in, configure: Regenderated.
* config/rs6000/power4.md: Add mfcrf reservation.
* config/rs6000/rs6000-protos.h (mfcr_operation): Declare.
* config/rs6000/rs6000.c (mfcr_operation): Define.
(print_operand): Add 'Q' case for mfcrf.
* config/rs6000/rs6000.h (TARGET_MFCRF): New.
* config/rs6000/rs6000.md (attribute "type"): Add mfcrf.
(movcc_internal1): Emit optional field operand for mfcr and set
"type" attribute appropriately.
(mfcr SCC): Likewise.
(movesi_from_cr_one): New.
Co-Authored-By: Fariborz Jahanian <fjahanian@apple.com>
From-SVN: r69064
This commit is contained in:
David Edelsohn
David Edelsohn
parent
ee76b9314b
commit
2c4a9cffc1
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@ -1,3 +1,20 @@
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2003-07-07 David Edelsohn <edelsohn@gnu.org>
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Fariborz Jahanian <fjahanian@apple.com>
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* configure.in: Test for PowerPC mfcr field support in assembler.
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* config.in, configure: Regenderated.
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* config/rs6000/power4.md: Add mfcrf reservation.
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* config/rs6000/rs6000-protos.h (mfcr_operation): Declare.
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* config/rs6000/rs6000.c (mfcr_operation): Define.
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(print_operand): Add 'Q' case for mfcrf.
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* config/rs6000/rs6000.h (TARGET_MFCRF): New.
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* config/rs6000/rs6000.md (attribute "type"): Add mfcrf.
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(movcc_internal1): Emit optional field operand for mfcr and set
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"type" attribute appropriately.
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(mfcr SCC): Likewise.
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(movesi_from_cr_one): New.
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2003-07-07 Roger Sayle <roger@eyesopen.com>
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* config/i386/i386.md: Correct check-in of incorrect version.
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@ -572,6 +572,9 @@
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/* Define if your assembler supports ltoffx and ldxmov relocations. */
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#undef HAVE_AS_LTOFFX_LDXMOV_RELOCS
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/* Define if your assembler supports mfcr field. */
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#undef HAVE_AS_MFCRF
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/* Define if your assembler supports dwarf2 .file/.loc directives,
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and preserves file table indices exactly as given. */
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#undef HAVE_AS_DWARF2_DEBUG_LINE
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@ -202,7 +202,7 @@
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|(du2_power4+du3_power4,iu2_power4,iu2_power4)\
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|(du3_power4+du4_power4,nothing,iu2_power4,iu1_power4)")
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(define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr")
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(define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
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(define_insn_reservation "power4-lmul-cmp" 7
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(and (eq_attr "type" "lmul_compare")
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@ -212,7 +212,7 @@
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|(du3_power4+du4_power4,iu2_power4*6,iu1_power4)")
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; |(du3_power4+du4_power4,nothing,iu2_power4*6,iu1_power4)")
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(define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr")
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(define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
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(define_insn_reservation "power4-imul-cmp" 5
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(and (eq_attr "type" "imul_compare")
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@ -222,7 +222,7 @@
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|(du3_power4+du4_power4,iu2_power4*4,iu1_power4)")
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; |(du3_power4+du4_power4,nothing,iu2_power4*4,iu1_power4)")
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(define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr")
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(define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
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(define_insn_reservation "power4-lmul" 7
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(and (eq_attr "type" "lmul")
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@ -305,6 +305,12 @@
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du1_power4+du2_power4+du3_power4+du4_power4+cru_power4,\
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cru_power4,cru_power4,cru_power4")
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; mfcrf (1 field)
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(define_insn_reservation "power4-mfcrf" 3
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(and (eq_attr "type" "mfcrf")
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(eq_attr "cpu" "power4"))
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"du1_power4,cru_power4")
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; mtcrf (1 field)
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(define_insn_reservation "power4-mtcr" 4
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(and (eq_attr "type" "mtcr")
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@ -379,7 +385,7 @@
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(define_bypass 9 "power4-vecfloat" "power4-vecperm")
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(define_bypass 5 "power4-vecsimple,power4-veccomplex"
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"power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr")
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"power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
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(define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore")
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(define_bypass 7 "power4-veccomplex" "power4-vecstore")
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@ -122,6 +122,7 @@ extern void rs6000_initialize_trampoline PARAMS ((rtx, rtx, rtx));
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extern struct rtx_def *rs6000_longcall_ref PARAMS ((rtx));
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extern void rs6000_fatal_bad_address PARAMS ((rtx));
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extern int stmw_operation PARAMS ((rtx, enum machine_mode));
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extern int mfcr_operation PARAMS ((rtx, enum machine_mode));
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extern int mtcrf_operation PARAMS ((rtx, enum machine_mode));
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extern int lmw_operation PARAMS ((rtx, enum machine_mode));
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extern struct rtx_def *create_TOC_reference PARAMS ((rtx));
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@ -7294,6 +7294,56 @@ vrsave_operation (op, mode)
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return 1;
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}
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/* Return 1 for an PARALLEL suitable for mfcr. */
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int
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mfcr_operation (op, mode)
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rtx op;
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enum machine_mode mode ATTRIBUTE_UNUSED;
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{
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int count = XVECLEN (op, 0);
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int i;
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/* Perform a quick check so we don't blow up below. */
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if (count < 1
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|| GET_CODE (XVECEXP (op, 0, 0)) != SET
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|| GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
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|| XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
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return 0;
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for (i = 0; i < count; i++)
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{
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rtx exp = XVECEXP (op, 0, i);
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rtx unspec;
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int maskval;
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rtx src_reg;
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src_reg = XVECEXP (SET_SRC (exp), 0, 0);
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if (GET_CODE (src_reg) != REG
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|| GET_MODE (src_reg) != CCmode
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|| ! CR_REGNO_P (REGNO (src_reg)))
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return 0;
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if (GET_CODE (exp) != SET
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|| GET_CODE (SET_DEST (exp)) != REG
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|| GET_MODE (SET_DEST (exp)) != SImode
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|| ! INT_REGNO_P (REGNO (SET_DEST (exp))))
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return 0;
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unspec = SET_SRC (exp);
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maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
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if (GET_CODE (unspec) != UNSPEC
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|| XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
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|| XVECLEN (unspec, 0) != 2
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|| XVECEXP (unspec, 0, 0) != src_reg
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|| GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
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|| INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
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return 0;
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}
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return 1;
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}
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/* Return 1 for an PARALLEL suitable for mtcrf. */
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int
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@ -8499,6 +8549,13 @@ print_operand (file, x, code)
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}
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return;
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case 'Q':
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if (TARGET_MFCRF)
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fputc (',',file);
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/* FALLTHRU */
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else
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return;
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case 'R':
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/* X is a CR register. Print the mask for `mtcrf'. */
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if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
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@ -13198,7 +13255,8 @@ rs6000_variable_issue (stream, verbose, insn, more)
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{
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enum attr_type type = get_attr_type (insn);
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if (type == TYPE_LOAD_EXT_U || type == TYPE_LOAD_EXT_UX
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|| type == TYPE_LOAD_UX || type == TYPE_STORE_UX)
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|| type == TYPE_LOAD_UX || type == TYPE_STORE_UX
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|| type == TYPE_MFCR)
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return 0;
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else if (type == TYPE_LOAD_U || type == TYPE_STORE_U
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|| type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
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@ -475,6 +475,16 @@ extern int rs6000_alignment_flags;
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#define TARGET_ALIGN_NATURAL 0
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#endif
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/* Define TARGET_MFCRF if the target assembler supports the optional
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field operand for mfcr and the target processor supports the
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instruction. */
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#ifdef HAVE_AS_MFCRF
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#define TARGET_MFCRF (rs6000_cpu == PROCESSOR_POWER4)
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#else
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#define TARGET_MFCRF 0
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#endif
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#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
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#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
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#define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
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@ -62,7 +62,7 @@
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;; Define an insn type attribute. This is used in function unit delay
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;; computations.
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(define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
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(define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
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(const_string "integer"))
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;; Length (in bytes).
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@ -7800,15 +7800,33 @@
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mcrf %0,%1
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mtcrf 128,%1
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{rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
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mfcr %0
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mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
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mfcr %0%Q1
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mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
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mr %0,%1
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mf%1 %0
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mt%0 %1
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mt%0 %1
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{l%U1%X1|lwz%U1%X1} %0,%1
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{st%U0%U1|stw%U0%U1} %1,%0"
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[(set_attr "type" "cr_logical,mtcr,mtcr,mfcr,mfcr,*,mfjmpr,*,mtjmpr,load,store")
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[(set (attr "type")
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(cond [(eq_attr "alternative" "0")
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(const_string "cr_logical")
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(eq_attr "alternative" "1,2")
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(const_string "mtcr")
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(eq_attr "alternative" "5,7")
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(const_string "integer")
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(eq_attr "alternative" "6")
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(const_string "mfjmpr")
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(eq_attr "alternative" "8")
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(const_string "mtjmpr")
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(eq_attr "alternative" "9")
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(const_string "load")
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(eq_attr "alternative" "10")
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(const_string "store")
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(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
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(const_string "mfcrf")
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]
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(const_string "mfcr")))
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(set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
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;; For floating-point, we normally deal with the floating-point registers
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@ -11368,8 +11386,12 @@
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[(match_operand 2 "cc_reg_operand" "y")
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(const_int 0)]))]
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""
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"mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
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[(set_attr "type" "mfcr")
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"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
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[(set (attr "type")
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(cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
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(const_string "mfcrf")
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]
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(const_string "mfcr")))
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(set_attr "length" "12")])
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;; Same as above, but get the OV/ORDERED bit.
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@ -11387,8 +11409,12 @@
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[(match_operand 2 "cc_reg_operand" "y")
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(const_int 0)]))]
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"TARGET_POWERPC64"
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"mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
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[(set_attr "type" "mfcr")
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"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
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[(set (attr "type")
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(cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
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(const_string "mfcrf")
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]
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(const_string "mfcr")))
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(set_attr "length" "12")])
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(define_insn ""
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@ -11401,7 +11427,7 @@
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(match_op_dup 1 [(match_dup 2) (const_int 0)]))]
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"! TARGET_POWERPC64"
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"@
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mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1
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mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
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#"
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[(set_attr "type" "delayed_compare")
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(set_attr "length" "12,16")])
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@ -11443,9 +11469,13 @@
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operands[4] = GEN_INT (count);
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operands[5] = GEN_INT (put_bit);
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return \"mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
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return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
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}"
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[(set_attr "type" "mfcr")
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[(set (attr "type")
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(cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
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(const_string "mfcrf")
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]
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(const_string "mfcr")))
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(set_attr "length" "12")])
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(define_insn ""
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@ -11478,7 +11508,7 @@
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operands[5] = GEN_INT (count);
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operands[6] = GEN_INT (put_bit);
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return \"mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
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return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
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}"
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[(set_attr "type" "delayed_compare")
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(set_attr "length" "12,16")])
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@ -14434,6 +14464,27 @@
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DONE;
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}")
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(define_insn "*movesi_from_cr_one"
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[(match_parallel 0 "mfcr_operation"
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[(set (match_operand:SI 1 "gpc_reg_operand" "=r")
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(unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
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(match_operand 3 "immediate_operand" "n")]
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UNSPEC_MOVESI_FROM_CR))])]
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"TARGET_MFCRF"
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"*
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{
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int mask = 0;
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int i;
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for (i = 0; i < XVECLEN (operands[0], 0); i++)
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{
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mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
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operands[4] = GEN_INT (mask);
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output_asm_insn (\"mfcr %1,%4\", operands);
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}
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return \"\";
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}"
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[(set_attr "type" "mfcrf")])
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(define_insn "movesi_from_cr"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
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|
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@ -8319,6 +8319,55 @@ echo "$ac_t""$gcc_cv_as_ltoffx_ldxmov_relocs" 1>&6
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if test "x$gcc_cv_as_ltoffx_ldxmov_relocs" = xyes; then
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cat >> confdefs.h <<\EOF
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#define HAVE_AS_LTOFFX_LDXMOV_RELOCS 1
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EOF
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fi
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;;
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powerpc*-*-*)
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echo $ac_n "checking assembler supports mfcr field""... $ac_c" 1>&6
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echo "configure:8174: checking assembler supports mfcr field" >&5
|
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if eval "test \"`echo '$''{'gcc_cv_as_mfcrf'+set}'`\" = set"; then
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echo $ac_n "(cached) $ac_c" 1>&6
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else
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|
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gcc_cv_as_mfcrf=unknown
|
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if test $in_tree_gas = yes ; then
|
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if test $gcc_cv_gas_major_version -eq 2 \
|
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&& test $gcc_cv_gas_minor_version -ge 14 \
|
||||
|| test $gcc_cv_gas_major_version -gt 2 ; then
|
||||
|
||||
|
||||
gcc_cv_as_mfcrf=yes
|
||||
|
||||
|
||||
fi
|
||||
|
||||
elif test x$gcc_cv_as != x; then
|
||||
cat > conftest.s << 'EOF'
|
||||
case "$target" in
|
||||
*-*-aix*)
|
||||
.csect .text[PR]
|
||||
;;
|
||||
*)
|
||||
.text
|
||||
;;
|
||||
esac
|
||||
mfcr 3,128
|
||||
EOF
|
||||
if $gcc_cv_as -o conftest.o conftest.s > /dev/null 2>&1; then
|
||||
gcc_cv_as_mfcrf=yes
|
||||
else
|
||||
gcc_cv_as_mfcrf=no
|
||||
fi
|
||||
rm -f conftest.s conftest.o
|
||||
fi
|
||||
|
||||
fi
|
||||
|
||||
echo "$ac_t""$gcc_cv_as_mfcrf" 1>&6
|
||||
if test "x$gcc_cv_as_mfcrf" = xyes; then
|
||||
cat >> confdefs.h <<\EOF
|
||||
#define HAVE_AS_MFCRF 1
|
||||
EOF
|
||||
|
||||
fi
|
||||
|
|
|
|||
|
|
@ -2462,6 +2462,41 @@ changequote([,])dnl
|
|||
[Define if your assembler supports ltoffx and ldxmov relocations.])
|
||||
fi
|
||||
;;
|
||||
powerpc*-*-*)
|
||||
AC_CACHE_CHECK([assembler supports mfcr field],
|
||||
gcc_cv_as_mfcrf, [
|
||||
gcc_cv_as_mfcrf=unknown
|
||||
if test $in_tree_gas = yes ; then
|
||||
gcc_GAS_VERSION_GTE_IFELSE(2,14,0,[
|
||||
gcc_cv_as_mfcrf=yes
|
||||
])
|
||||
elif test x$gcc_cv_as != x; then
|
||||
cat > conftest.s << 'EOF'
|
||||
case "$target" in
|
||||
changequote(,)dnl
|
||||
*-*-aix*)
|
||||
.csect .text[PR]
|
||||
;;
|
||||
*)
|
||||
.text
|
||||
;;
|
||||
esac
|
||||
mfcr 3,128
|
||||
EOF
|
||||
changequote([,])dnl
|
||||
if $gcc_cv_as -o conftest.o conftest.s > /dev/null 2>&1; then
|
||||
gcc_cv_as_mfcrf=yes
|
||||
else
|
||||
gcc_cv_as_mfcrf=no
|
||||
fi
|
||||
rm -f conftest.s conftest.o
|
||||
fi
|
||||
])
|
||||
if test "x$gcc_cv_as_mfcrf" = xyes; then
|
||||
AC_DEFINE(HAVE_AS_MFCRF, 1,
|
||||
[Define if your assembler supports mfcr field.])
|
||||
fi
|
||||
;;
|
||||
esac
|
||||
|
||||
AC_MSG_CHECKING(assembler dwarf2 debug_line support)
|
||||
|
|
|
|||
Loading…
Reference in New Issue