re PR target/54061 (gcc.c-torture/compile/mipscop-*.c ICEs with -g)
2012-12-10 Steve Ellcey <sellcey@mips.com> PR target/54061 rtl.h (IGNORED_DWARF_REGNUM): New. * dwarf2out.c (reg_loc_descriptor): Check for IGNORED_DWARF_REGNUM. (mem_loc_descriptor): Ditto. * config/mips/mips.h (ALL_COP_REG_FIRST): New. (ALL_COP_REG_LAST): New. (ALL_COP_REG_NUM): Redefine using above macros. * config/mips/mips.c (mips_option_override): Set mips_dbx_regno coprocessor entries to IGNORED_DWARF_REGNUM. From-SVN: r194372
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@ -1,3 +1,15 @@
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2012-12-10 Steve Ellcey <sellcey@mips.com>
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PR target/54061
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rtl.h (IGNORED_DWARF_REGNUM): New.
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* dwarf2out.c (reg_loc_descriptor): Check for IGNORED_DWARF_REGNUM.
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(mem_loc_descriptor): Ditto.
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* config/mips/mips.h (ALL_COP_REG_FIRST): New.
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(ALL_COP_REG_LAST): New.
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(ALL_COP_REG_NUM): Redefine using above macros.
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* config/mips/mips.c (mips_option_override): Set mips_dbx_regno
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coprocessor entries to IGNORED_DWARF_REGNUM.
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2012-12-10 H.J. Lu <hongjiu.lu@intel.com>
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PR lto/55466
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@ -16757,6 +16757,9 @@ mips_option_override (void)
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for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
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mips_dbx_regno[i] = i + start;
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for (i = ALL_COP_REG_FIRST; i <= ALL_COP_REG_LAST; i++)
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mips_dbx_regno[i] = IGNORED_DWARF_REGNUM;
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/* Accumulator debug registers use big-endian ordering. */
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mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
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mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
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@ -1641,8 +1641,11 @@ struct mips_cpu_info {
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#define COP3_REG_FIRST 144
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#define COP3_REG_LAST 175
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#define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
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/* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
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#define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
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/* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
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#define ALL_COP_REG_FIRST COP0_REG_FIRST
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#define ALL_COP_REG_LAST COP3_REG_LAST
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#define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
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#define DSP_ACC_REG_FIRST 176
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#define DSP_ACC_REG_LAST 181
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@ -10499,7 +10499,12 @@ reg_loc_descriptor (rtx rtl, enum var_init_status initialized)
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if (hard_regno_nregs[REGNO (rtl)][GET_MODE (rtl)] > 1 || regs)
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return multiple_reg_loc_descriptor (rtl, regs, initialized);
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else
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return one_reg_loc_descriptor (dbx_reg_number (rtl), initialized);
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{
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unsigned int dbx_regnum = dbx_reg_number (rtl);
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if (dbx_regnum == IGNORED_DWARF_REGNUM)
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return 0;
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return one_reg_loc_descriptor (dbx_regnum, initialized);
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}
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}
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/* Return a location descriptor that designates a machine register for
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@ -11926,6 +11931,7 @@ mem_loc_descriptor (rtx rtl, enum machine_mode mode,
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))
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{
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dw_die_ref type_die;
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unsigned int dbx_regnum;
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if (dwarf_strict)
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break;
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@ -11935,8 +11941,12 @@ mem_loc_descriptor (rtx rtl, enum machine_mode mode,
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GET_MODE_CLASS (mode) == MODE_INT);
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if (type_die == NULL)
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break;
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dbx_regnum = dbx_reg_number (rtl);
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if (dbx_regnum == IGNORED_DWARF_REGNUM)
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break;
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mem_loc_result = new_loc_descr (DW_OP_GNU_regval_type,
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dbx_reg_number (rtl), 0);
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dbx_regnum, 0);
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mem_loc_result->dw_loc_oprnd2.val_class = dw_val_class_die_ref;
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mem_loc_result->dw_loc_oprnd2.v.val_die_ref.die = type_die;
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mem_loc_result->dw_loc_oprnd2.v.val_die_ref.external = 0;
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@ -12138,9 +12148,13 @@ mem_loc_descriptor (rtx rtl, enum machine_mode mode,
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op0 = mem_loc_descriptor (ENTRY_VALUE_EXP (rtl), mode,
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VOIDmode, VAR_INIT_STATUS_INITIALIZED);
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else
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op0
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= one_reg_loc_descriptor (dbx_reg_number (ENTRY_VALUE_EXP (rtl)),
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VAR_INIT_STATUS_INITIALIZED);
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{
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unsigned int dbx_regnum = dbx_reg_number (ENTRY_VALUE_EXP (rtl));
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if (dbx_regnum == IGNORED_DWARF_REGNUM)
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return NULL;
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op0 = one_reg_loc_descriptor (dbx_regnum,
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VAR_INIT_STATUS_INITIALIZED);
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}
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}
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else if (MEM_P (ENTRY_VALUE_EXP (rtl))
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&& REG_P (XEXP (ENTRY_VALUE_EXP (rtl), 0)))
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@ -2439,6 +2439,9 @@ extern rtx gen_rtx_MEM (enum machine_mode, rtx);
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/* REGNUM never really appearing in the INSN stream. */
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#define INVALID_REGNUM (~(unsigned int) 0)
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/* REGNUM for which no debug information can be generated. */
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#define IGNORED_DWARF_REGNUM (INVALID_REGNUM - 1)
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extern rtx output_constant_def (tree, int);
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extern rtx lookup_constant_def (tree);
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