re PR target/12902 (Invalid assembly generated when using SSE / xmmintrin.h)
PR target/12902
* config/i386/i386.md (sse_movhps, sse_movlps): Remove.
(sse_shufps): Change operand 3 to const_int_operand.
(sse2_storelps): Fix typo in template.
(sse_storehps, sse_loadhps, sse_storelps, sse_loadlps): New.
* config/i386/i386.c (ix86_expand_vector_move_misalign): Use them.
(ix86_expand_builtin): Likewise.
From-SVN: r92967
This commit is contained in:
Richard Henderson
parent
a8182d3719
commit
2cdb314898
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@ -1,4 +1,14 @@
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2004-01-05 Julian Brown <julian@codesourcery.com>
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2005-01-05 Richard Henderson <rth@redhat.com>
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PR target/12902
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* config/i386/i386.md (sse_movhps, sse_movlps): Remove.
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(sse_shufps): Change operand 3 to const_int_operand.
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(sse2_storelps): Fix typo in template.
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(sse_storehps, sse_loadhps, sse_storelps, sse_loadlps): New.
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* config/i386/i386.c (ix86_expand_vector_move_misalign): Use them.
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(ix86_expand_builtin): Likewise.
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2005-01-05 Julian Brown <julian@codesourcery.com>
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* config/arm/arm.c (arm_return_in_memory): Treat complex types
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as aggregates for AAPCS ABIs.
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@ -1,6 +1,6 @@
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/* Subroutines used for code generation on IA-32.
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Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
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2002, 2003, 2004 Free Software Foundation, Inc.
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2002, 2003, 2004, 2005 Free Software Foundation, Inc.
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This file is part of GCC.
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@ -7645,11 +7645,10 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
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else
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emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
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op0 = gen_lowpart (V4SFmode, op0);
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m = adjust_address (op1, V4SFmode, 0);
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emit_insn (gen_sse_movlps (op0, op0, m));
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m = adjust_address (op1, V4SFmode, 8);
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emit_insn (gen_sse_movhps (op0, op0, m));
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m = adjust_address (op1, V2SFmode, 0);
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emit_insn (gen_sse_loadlps (op0, op0, m));
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m = adjust_address (op1, V2SFmode, 8);
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emit_insn (gen_sse_loadhps (op0, op0, m));
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}
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}
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else if (MEM_P (op0))
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@ -7684,11 +7683,10 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
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}
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else
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{
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op1 = gen_lowpart (V4SFmode, op1);
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m = adjust_address (op0, V4SFmode, 0);
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emit_insn (gen_sse_movlps (m, m, op1));
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m = adjust_address (op0, V4SFmode, 8);
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emit_insn (gen_sse_movhps (m, m, op1));
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m = adjust_address (op0, V2SFmode, 0);
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emit_insn (gen_sse_storelps (m, op1));
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m = adjust_address (op0, V2SFmode, 8);
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emit_insn (gen_sse_storehps (m, op1));
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return;
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}
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}
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@ -13508,8 +13506,8 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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case IX86_BUILTIN_LOADLPS:
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case IX86_BUILTIN_LOADHPD:
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case IX86_BUILTIN_LOADLPD:
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icode = (fcode == IX86_BUILTIN_LOADHPS ? CODE_FOR_sse_movhps
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: fcode == IX86_BUILTIN_LOADLPS ? CODE_FOR_sse_movlps
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icode = (fcode == IX86_BUILTIN_LOADHPS ? CODE_FOR_sse_loadhps
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: fcode == IX86_BUILTIN_LOADLPS ? CODE_FOR_sse_loadlps
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: fcode == IX86_BUILTIN_LOADHPD ? CODE_FOR_sse2_loadhpd
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: CODE_FOR_sse2_loadlpd);
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arg0 = TREE_VALUE (arglist);
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@ -13535,28 +13533,11 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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case IX86_BUILTIN_STOREHPS:
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case IX86_BUILTIN_STORELPS:
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icode = (fcode == IX86_BUILTIN_STOREHPS ? CODE_FOR_sse_movhps
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: CODE_FOR_sse_movlps);
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arg0 = TREE_VALUE (arglist);
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arg1 = TREE_VALUE (TREE_CHAIN (arglist));
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op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
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op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
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mode0 = insn_data[icode].operand[1].mode;
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mode1 = insn_data[icode].operand[2].mode;
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op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
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if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
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op1 = copy_to_mode_reg (mode1, op1);
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pat = GEN_FCN (icode) (op0, op0, op1);
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if (! pat)
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return 0;
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emit_insn (pat);
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return const0_rtx;
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case IX86_BUILTIN_STOREHPD:
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case IX86_BUILTIN_STORELPD:
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icode = (fcode == IX86_BUILTIN_STOREHPD ? CODE_FOR_sse2_storehpd
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icode = (fcode == IX86_BUILTIN_STOREHPS ? CODE_FOR_sse_storehps
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: fcode == IX86_BUILTIN_STORELPS ? CODE_FOR_sse_storelps
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: fcode == IX86_BUILTIN_STOREHPD ? CODE_FOR_sse2_storehpd
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: CODE_FOR_sse2_storelpd);
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arg0 = TREE_VALUE (arglist);
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arg1 = TREE_VALUE (TREE_CHAIN (arglist));
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@ -1,6 +1,6 @@
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;; GCC machine description for IA-32 and x86-64.
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;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
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;; 2001, 2002, 2003, 2004
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;; 2001, 2002, 2003, 2004, 2005
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;; Free Software Foundation, Inc.
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;; Mostly by William Schelter.
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;; x86_64 support added by Jan Hubicka
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@ -20335,29 +20335,98 @@
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[(set_attr "type" "ssecvt")
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(set_attr "mode" "V4SF")])
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(define_insn "sse_movhps"
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[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
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(vec_merge:V4SF
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(match_operand:V4SF 1 "nonimmediate_operand" "0,0")
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(match_operand:V4SF 2 "nonimmediate_operand" "m,x")
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(const_int 12)))]
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"TARGET_SSE
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&& (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
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"movhps\t{%2, %0|%0, %2}"
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;; Store the high V2SF of the source vector to the destination.
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(define_insn "sse_storehps"
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[(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
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(vec_select:V2SF
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(match_operand:V4SF 1 "nonimmediate_operand" "x,x,o")
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(parallel [(const_int 2) (const_int 3)])))]
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"TARGET_SSE"
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"@
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movhps\t{%1, %0|%0, %1}
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movhlps\t{%1, %0|%0, %1}
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#"
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[(set_attr "type" "ssecvt")
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(set_attr "mode" "V4SF")])
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(set_attr "mode" "V2SF")])
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(define_insn "sse_movlps"
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[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
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(vec_merge:V4SF
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(match_operand:V4SF 1 "nonimmediate_operand" "0,0")
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(match_operand:V4SF 2 "nonimmediate_operand" "m,x")
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(const_int 3)))]
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"TARGET_SSE
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&& (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
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"movlps\t{%2, %0|%0, %2}"
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(define_split
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[(set (match_operand:V2SF 0 "register_operand" "")
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(vec_select:V2SF
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(match_operand:V4SF 1 "memory_operand" "")
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(parallel [(const_int 2) (const_int 3)])))]
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"TARGET_SSE && reload_completed"
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[(const_int 0)]
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{
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emit_move_insn (operands[0], adjust_address (operands[1], V2SFmode, 8));
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DONE;
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})
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;; Load the high V2SF of the target vector from the source vector.
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(define_insn "sse_loadhps"
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[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
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(vec_concat:V4SF
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(vec_select:V2SF
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(match_operand:V4SF 1 "nonimmediate_operand" "0,0,0")
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(parallel [(const_int 0) (const_int 1)]))
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(match_operand:V2SF 2 "nonimmediate_operand" "m,x,x")))]
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"TARGET_SSE"
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"@
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movhps\t{%2, %0|%0, %2}
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movlhps\t{%2, %0|%0, %2}
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#"
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[(set_attr "type" "ssecvt")
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(set_attr "mode" "V4SF")])
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(set_attr "mode" "V2SF")])
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(define_split
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[(set (match_operand:V4SF 0 "memory_operand" "")
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(vec_concat:V4SF
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(vec_select:V2SF
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(match_dup 0)
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(parallel [(const_int 0) (const_int 1)]))
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(match_operand:V2SF 2 "register_operand" "")))]
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"TARGET_SSE && reload_completed"
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[(const_int 0)]
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{
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emit_move_insn (adjust_address (operands[0], V2SFmode, 8), operands[1]);
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DONE;
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})
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;; Store the low V2SF of the source vector to the destination.
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(define_expand "sse_storelps"
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[(set (match_operand:V2SF 0 "nonimmediate_operand" "")
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(vec_select:V2SF
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(match_operand:V4SF 1 "nonimmediate_operand" "")
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(parallel [(const_int 0) (const_int 1)])))]
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"TARGET_SSE"
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{
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operands[1] = gen_lowpart (V2SFmode, operands[1]);
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emit_move_insn (operands[0], operands[1]);
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DONE;
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})
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;; Load the low V2SF of the target vector from the source vector.
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(define_insn "sse_loadlps"
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[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
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(vec_concat:V4SF
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(match_operand:V2SF 2 "nonimmediate_operand" "m,0,x")
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(vec_select:V2SF
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(match_operand:V4SF 1 "nonimmediate_operand" "0,x,0")
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(parallel [(const_int 2) (const_int 3)]))))]
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"TARGET_SSE"
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{
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static const char * const alt[] = {
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"movlps\t{%2, %0|%0, %2}",
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"shufps\t{%2, %1, %0|%0, %1, %2}",
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"movlps\t{%2, %0|%0, %2}"
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};
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if (which_alternative == 1)
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operands[2] = GEN_INT (0xe4);
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return alt[which_alternative];
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}
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[(set_attr "type" "ssecvt")
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(set_attr "mode" "V2SF")])
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(define_expand "sse_loadss"
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[(match_operand:V4SF 0 "register_operand" "")
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@ -20405,10 +20474,9 @@
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[(set (match_operand:V4SF 0 "register_operand" "=x")
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(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
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(match_operand:V4SF 2 "nonimmediate_operand" "xm")
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(match_operand:SI 3 "immediate_operand" "i")]
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(match_operand:SI 3 "const_int_operand" "n")]
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UNSPEC_SHUFFLE))]
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"TARGET_SSE"
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;; @@@ check operand order for intel/nonintel syntax
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"shufps\t{%3, %2, %0|%0, %2, %3}"
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[(set_attr "type" "ssecvt")
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(set_attr "mode" "V4SF")])
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@ -23902,7 +23970,7 @@
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[(set (match_operand:DF 0 "nonimmediate_operand" "")
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(vec_select:DF
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(match_operand:V2DF 1 "nonimmediate_operand" "")
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(parallel [(const_int 1)])))]
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(parallel [(const_int 0)])))]
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"TARGET_SSE2"
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{
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operands[1] = gen_lowpart (DFmode, operands[1]);
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@ -23910,7 +23978,7 @@
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DONE;
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})
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;; Load the load double of the target vector from the source scalar.
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;; Load the low double of the target vector from the source scalar.
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(define_insn "sse2_loadlpd"
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[(set (match_operand:V2DF 0 "nonimmediate_operand" "=Y,Y,m")
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(vec_concat:V2DF
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@ -0,0 +1,25 @@
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/* PR 12902 */
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/* { dg-do compile } */
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/* { dg-options "-O1 -msse" } */
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#include <xmmintrin.h>
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typedef union
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{
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int i[4];
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float f[4];
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__m128 v;
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} vector4_t;
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void
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swizzle (const void *a, vector4_t * b, vector4_t * c)
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{
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b->v = _mm_loadl_pi (b->v, (__m64 *) a);
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c->v = _mm_loadl_pi (c->v, ((__m64 *) a) + 1);
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}
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/* While one legal rendering of each statement would be movaps;movlps;movaps,
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we can implmenent this with just movlps;movlps. Since we do now, anything
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less would be a regression. */
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/* { dg-final { scan-assembler-not "movaps" } } */
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/* { dg-final { scan-assembler "movlps" } } */
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